From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Tue, 6 Mar 2012 15:45:44 +0000 (+0100)
Subject: fhdl/verilog: fix signed constant conversion
X-Git-Tag: 24jan2021_ls180~2099^2~991
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=90184b22d2f7e88fd4e76ae142480756038ef2cc;p=litex.git

fhdl/verilog: fix signed constant conversion
---

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index e68071ae..854da372 100644
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -21,7 +21,7 @@ def _printexpr(ns, node):
 		if node.n >= 0:
 			return str(node.bv) + str(node.n)
 		else:
-			return "-" + str(node.bv) + str(-self.n)
+			return "-" + str(node.bv) + str(-node.n)
 	elif isinstance(node, Signal):
 		return ns.get_name(node)
 	elif isinstance(node, _Operator):