From: Luke Kenneth Casson Leighton Date: Wed, 14 Jul 2021 19:07:02 +0000 (+0100) Subject: update SVSTATE to 64 bit length (fortunately very easy) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=90227c647aab03544a837defed874d6e0fa05a58;p=soc.git update SVSTATE to 64 bit length (fortunately very easy) --- diff --git a/src/soc/fu/trap/pipe_data.py b/src/soc/fu/trap/pipe_data.py index 44c63654..93a135b8 100644 --- a/src/soc/fu/trap/pipe_data.py +++ b/src/soc/fu/trap/pipe_data.py @@ -27,7 +27,7 @@ class TrapOutputData(FUBaseData): # ... however we *do* need to *write* MSR, NIA, SVSTATE (RFID) ('STATE', 'nia', '0:63'), # NIA (Next PC) ('STATE', 'msr', '0:63'), # MSR - ('STATE', 'svstate', '0:31')] # SVSTATE + ('STATE', 'svstate', '0:63')] # SVSTATE def __init__(self, pspec): super().__init__(pspec, True) # convenience diff --git a/src/soc/fu/trap/trap_input_record.py b/src/soc/fu/trap/trap_input_record.py index 4d3d66e8..521ab590 100644 --- a/src/soc/fu/trap/trap_input_record.py +++ b/src/soc/fu/trap/trap_input_record.py @@ -16,7 +16,7 @@ class CompTrapOpSubset(CompOpSubsetBase): ('insn', 32), ('msr', 64), # from core.state ('cia', 64), # likewise - ('svstate', 32), # likewise + ('svstate', 64), # likewise ('is_32bit', 1), ('traptype', TT.size), # see trap main_stage.py, PowerDecoder2 ('trapaddr', 13), diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 465ade0e..feef6b62 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -242,7 +242,7 @@ class TestIssuerInternal(Elaboratable): # instruction go/monitor self.pc_o = Signal(64, reset_less=True) self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me" - self.svstate_i = Data(32, "svstate_i") # ditto + self.svstate_i = Data(64, "svstate_i") # ditto self.core_bigendian_i = Signal() # TODO: set based on MSR.LE self.busy_o = Signal(reset_less=True) self.memerr_o = Signal(reset_less=True) diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py index 85afa309..180474e1 100644 --- a/src/soc/simple/test/test_runner.py +++ b/src/soc/simple/test/test_runner.py @@ -134,7 +134,7 @@ class TestRunner(FHDLTestCase): m = Module() comb = m.d.comb pc_i = Signal(32) - svstate_i = Signal(32) + svstate_i = Signal(64) if self.microwatt_mmu: ldst_ifacetype = 'test_mmu_cache_wb'