From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 2 Jun 2020 21:59:34 +0000 (+0100)
Subject: take out unneeded code, add Settle() to see if it helps with bug
X-Git-Tag: div_pipeline~637^2~27
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9035c898eb9bcaf792df5d2a0e0de8848d4b64a6;p=soc.git

take out unneeded code, add Settle() to see if it helps with bug
---

diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py
index 605b9127..2c4b43e0 100644
--- a/src/soc/fu/compunits/test/test_compunit.py
+++ b/src/soc/fu/compunits/test/test_compunit.py
@@ -162,10 +162,7 @@ class TestRunner(FHDLTestCase):
                         fname = find_ok(wrok.fields)
                         yield getattr(wrok, fname).eq(0)
 
-                    # first set inputs to zero
-                    for idx in range(cu.n_src):
-                        cu_in = cu.get_in(idx)
-                        yield cu_in.eq(0)
+                    yield Settle()
 
                     # set inputs into CU
                     rd_rel_o = yield cu.rd.rel