From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 5 Jul 2022 17:57:07 +0000 (+0100)
Subject: converted test_caller_svp64_fp.py to new reg format
X-Git-Tag: sv_maxu_works-initial~295
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9069c3f850a5b867a53f60bef1c35dff7d0777fc;p=openpower-isa.git

converted test_caller_svp64_fp.py to new reg format
https://bugs.libre-soc.org/show_bug.cgi?id=884#c0
---

diff --git a/src/openpower/decoder/isa/test_caller_svp64_fp.py b/src/openpower/decoder/isa/test_caller_svp64_fp.py
index 51782281..7dda55a4 100644
--- a/src/openpower/decoder/isa/test_caller_svp64_fp.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_fp.py
@@ -23,10 +23,10 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
 
     def test_sv_fpload(self):
-        """>>> lst = ["sv.lfsx 2.v, 0, 0.v"
+        """>>> lst = ["sv.lfsx *2, 0, *0"
                         ]
         """
-        lst = SVP64Asm(["sv.lfsx 2.v, 0, 0.v"
+        lst = SVP64Asm(["sv.lfsx *2, 0, *0"
                         ])
         lst = list(lst)
 
@@ -58,9 +58,9 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.fpr(3), SelectableInt(0xC004000000000000, 64))
 
     def test_fp_single_ldst(self):
-        """>>> lst = ["sv.lfsx 0.v, 0, 4.v",   # load fp 1/2 from mem 0/8
-                      "sv.stfsu 0.v, 16(4.v)", # store fp 1/2, update RA *twice*
-                      "sv.lfs 2.v, 0(4.v)",   # re-load from UPDATED r4/r5
+        """>>> lst = ["sv.lfsx *0, 0, *4",   # load fp 1/2 from mem 0/8
+                      "sv.stfsu *0, 16(*4)", # store fp 1/2, update RA *twice*
+                      "sv.lfs *2, 0(*4)",   # re-load from UPDATED r4/r5
                      ]
 
         This is quite an involved (deceptively simple looking) test.
@@ -69,11 +69,11 @@ class DecoderTestCase(FHDLTestCase):
 
         Walkthrough:
 
-        1) sv.lfsx 0.v, 0, 4.v    VL=2 so there are *two* lfsx operations
+        1) sv.lfsx *0, 0, *4    VL=2 so there are *two* lfsx operations
                 lfsx 0, 0, 4      loads from MEM[GPR(4)], stores in FPR(0)
                 lfsx 1, 0, 5      loads from MEM[GPR(5)], stores in FPR(1)
 
-        2) sv.stfsu 0.v, 16(4.v)  again, VL=2 so there are two ST-FP-update ops
+        2) sv.stfsu *0, 16(*4)  again, VL=2 so there are two ST-FP-update ops
                 stfsu 0, 16(4)    EA=GPR(4)+16, FPR(0) to MEM[EA], EA to GPR(4)
                 stfsu 1, 16(5)    EA=GPR(5)+16, FPR(0) to MEM[EA], EA to GPR(5)
 
@@ -81,7 +81,7 @@ class DecoderTestCase(FHDLTestCase):
            writes of the calculated Effective Address to GPR, in regs 4 and 5
            GPRs 4 and 5 are *overwritten*.
 
-        3) sv.lfs 3.v, 0(4.v)     VL=2, so two immediate-LDs
+        3) sv.lfs *3, 0(*4)     VL=2, so two immediate-LDs
                 lfs 3, 0(4)       EA=GPR(4)+0, FPR(3) = MEM[EA]
                 lfs 4, 0(5)       EA=GPR(5)+0, FPR(4) = MEM[EA]
 
@@ -91,9 +91,9 @@ class DecoderTestCase(FHDLTestCase):
         of the memory locations 0x10 and 0x18, which should contain the
         single-precision FP numbers in the bottom 4 bytes.  TODO
         """
-        lst = SVP64Asm(["sv.lfsx 0.v, 0, 4.v",
-                        "sv.stfsu 0.v, 16(4.v)",
-                        "sv.lfs 2.v, 0(4.v)",
+        lst = SVP64Asm(["sv.lfsx *0, 0, *4",
+                        "sv.stfsu *0, 16(*4)",
+                        "sv.lfs *2, 0(*4)",
                      ])
         lst = list(lst)
 
@@ -132,10 +132,10 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.fpr(3), SelectableInt(0xC004000000000000, 64))
 
     def test_sv_fpadd(self):
-        """>>> lst = ["sv.fadds 6.v, 2.v, 4.v"
+        """>>> lst = ["sv.fadds *6, *2, *4"
                         ]
         """
-        lst = SVP64Asm(["sv.fadds 6.v, 2.v, 4.v"
+        lst = SVP64Asm(["sv.fadds *6, *2, *4"
                         ])
         lst = list(lst)
 
@@ -158,13 +158,13 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.fpr(7), SelectableInt(0xc050266660000000, 64))
 
     def test_sv_fpmadds(self):
-        """>>> lst = ["sv.fmadds 6.v, 2.v, 4.v, 8"
+        """>>> lst = ["sv.fmadds *6, *2, *4, 8"
                         ]
             two vector mul-adds with a scalar in f8
             * fp6 = fp2 * fp4 + f8 = 7.0 * 2.0 - 2.0 = 12.0
             * fp7 = fp3 * fp5 + f8 = 7.0 * 2.0 - 2.0 = 12.0
         """
-        lst = SVP64Asm(["sv.fmadds 6.v, 2.v, 4.v, 8"
+        lst = SVP64Asm(["sv.fmadds *6, *2, *4, 8"
                         ])
         lst = list(lst)