From: Ulrich Weigand <uweigand@de.ibm.com>
Date: Wed, 2 Jul 2008 15:38:44 +0000 (+0000)
Subject: 20030222-1.x: New file.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=906c5773db6775e8182c4ff74f5c835bca66ae4e;p=gcc.git

20030222-1.x: New file.

	* gcc.c-torture/execute/20030222-1.x: New file.
	* gcc.dg/tree-ssa/ssa-fre-3.c: Disable test on SPU.
	* gcc.dg/lower-subreg-1.c: Likewise.

From-SVN: r137360
---

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index e8175a12083..8a51dc0900d 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2008-07-02  Ulrich Weigand  <Ulrich.Weigand@de.ibm.com>
+
+	* gcc.c-torture/execute/20030222-1.x: New file.
+	* gcc.dg/tree-ssa/ssa-fre-3.c: Disable test on SPU.
+	* gcc.dg/lower-subreg-1.c: Likewise.
+
 2008-07-02  Ulrich Weigand  <Ulrich.Weigand@de.ibm.com>
 
 	SPU single-precision FP does not support subnormals:
diff --git a/gcc/testsuite/gcc.c-torture/execute/20030222-1.x b/gcc/testsuite/gcc.c-torture/execute/20030222-1.x
new file mode 100644
index 00000000000..e195563ddd0
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/20030222-1.x
@@ -0,0 +1,6 @@
+if [istarget "spu-*-*"] {
+    # Using inline assembly to convert long long to int is not working quite
+    # right # on the SPU.  An extra shift-left-4-byte is needed.
+    return 1
+}
+return 0
diff --git a/gcc/testsuite/gcc.dg/lower-subreg-1.c b/gcc/testsuite/gcc.dg/lower-subreg-1.c
index 01851268c11..bb35d21bb50 100644
--- a/gcc/testsuite/gcc.dg/lower-subreg-1.c
+++ b/gcc/testsuite/gcc.dg/lower-subreg-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { { ! mips64 } && { ! ia64-*-* } } } } */
+/* { dg-do compile { target { { { ! mips64 } && { ! ia64-*-* } } && { ! spu-*-* } } } } */
 /* { dg-options "-O -fdump-rtl-subreg" } */
 /* { dg-require-effective-target ilp32 } */
 
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c
index 3b7a547a6e7..85e444886d0 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c
@@ -5,7 +5,7 @@
 
    When the condition is true, we distribute "(int) (a + b)" as
    "(int) a + (int) b", otherwise we keep the original.  */
-/* { dg-do compile { target { ! mips64 } } } */
+/* { dg-do compile { target { { ! mips64 } && { ! spu-*-* } } } } */
 /* { dg-options "-O -fwrapv -fdump-tree-fre-details" } */
 
 /* From PR14844.  */