From: Luke Kenneth Casson Leighton Date: Fri, 12 Apr 2019 01:48:06 +0000 (+0100) Subject: add test23, connect FIFO-with-RecordObj to adder X-Git-Tag: ls180-24jan2020~1248 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=907201e32005066c4842e2ed9a7577738ffc2c8e;p=ieee754fpu.git add test23, connect FIFO-with-RecordObj to adder --- diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py index b8e6440f..651d907a 100644 --- a/src/add/test_buf_pipe.py +++ b/src/add/test_buf_pipe.py @@ -765,11 +765,10 @@ class ExampleBufPassThruPipe(ControlBase): ###################################################################### def iospecfn(): - return Signal(16, name="din") + return Signal(16, name="d_in") class FIFOTest16(FIFOControl): - def __init__(self): FIFOControl.__init__(self, iospecfn, 2) @@ -835,7 +834,36 @@ class ExampleRecordHandshakeAddClass(SimpleHandshake): # Test 23 ###################################################################### -def iospecfn22(): +def iospecfnrecord(): + return Example2OpRecord() + +class FIFOTestRecordControl(FIFOControl): + + def __init__(self): + FIFOControl.__init__(self, iospecfnrecord, 2) + + +class ExampleFIFORecordObjectPipe(ControlBase): + + def elaborate(self, platform): + m = ControlBase._elaborate(self, platform) + + pipe1 = FIFOTestRecordControl() + pipe2 = ExampleRecordHandshakeAddClass() + + m.submodules.pipe1 = pipe1 + m.submodules.pipe2 = pipe2 + + m.d.comb += self.connect([pipe1, pipe2]) + + return m + + +###################################################################### +# Test 24 +###################################################################### + +def iospecfn24(): return (Signal(16, name="src1"), Signal(16, name="src2")) class FIFOTest2x16(FIFOControl): @@ -1154,6 +1182,20 @@ if __name__ == '__main__': with open("test_addrecord22.il", "w") as f: f.write(vl) + + print ("test 23") + dut = ExampleFIFORecordObjectPipe() + data=data_2op() + test = Test5(dut, test8_resultfn, data=data) + run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord23.vcd") + ports = [dut.p.i_valid, dut.n.i_ready, + dut.n.o_valid, dut.p.o_ready] + \ + [dut.p.i_data.op1, dut.p.i_data.op2] + \ + [dut.n.o_data] + vl = rtlil.convert(dut, ports=ports) + with open("test_addrecord23.il", "w") as f: + f.write(vl) + print ("test 997") dut = ExampleBufPassThruPipe2() data = data_chain1()