From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 22 Sep 2021 23:05:07 +0000 (+0100)
Subject: add first "ExpectedState" to HDL-sim ALU test cases
X-Git-Tag: sv_maxu_works-initial~846
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=907570fdb16fa0baf737a79017b28ce4b980a926;p=openpower-isa.git

add first "ExpectedState" to HDL-sim ALU test cases
---

diff --git a/src/openpower/test/alu/alu_cases.py b/src/openpower/test/alu/alu_cases.py
index a4b32577..13efdd53 100644
--- a/src/openpower/test/alu/alu_cases.py
+++ b/src/openpower/test/alu/alu_cases.py
@@ -5,6 +5,7 @@ from openpower.simulator.program import Program
 from openpower.decoder.selectable_int import SelectableInt
 from openpower.decoder.power_enums import XER_bits
 from openpower.decoder.isa.caller import special_sprs
+from openpower.test.state import ExpectedState
 import unittest
 
 
@@ -109,7 +110,9 @@ class ALUTestCase(TestAccumulatorBase):
         print(lst)
         initial_regs = [0] * 32
         initial_regs[0] = 5
-        self.add_case(Program(lst, bigendian), initial_regs)
+        e = ExpectedState(initial_regs, pc=4)
+        e.intregs[3] = 0x10000
+        self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
     def case_addis_nonzero_r0(self):
         for i in range(10):