From: Sebastien Bourdeauducq Date: Tue, 12 Mar 2013 15:45:28 +0000 (+0100) Subject: examples/basic: use new APIs X-Git-Tag: 24jan2021_ls180~2099^2~653 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=907bfa87f44567526b408318da712cce1c687c35;p=litex.git examples/basic: use new APIs --- diff --git a/examples/basic/arrays.py b/examples/basic/arrays.py index 10b5530e..a041658f 100644 --- a/examples/basic/arrays.py +++ b/examples/basic/arrays.py @@ -1,25 +1,23 @@ from migen.fhdl.structure import * +from migen.fhdl.module import Module from migen.fhdl import verilog -dx = 5 -dy = 5 +class Example(Module): + def __init__(self): + dx = 5 + dy = 5 -x = Signal(max=dx) -y = Signal(max=dy) -out = Signal() + x = Signal(max=dx) + y = Signal(max=dy) + out = Signal() -my_2d_array = Array(Array(Signal() for a in range(dx)) for b in range(dy)) -comb = [ - out.eq(my_2d_array[x][y]) -] + my_2d_array = Array(Array(Signal() for a in range(dx)) for b in range(dy)) + self.comb += out.eq(my_2d_array[x][y]) -we = Signal() -inp = Signal() -sync = [ - If(we, - my_2d_array[x][y].eq(inp) - ) -] + we = Signal() + inp = Signal() + self.sync += If(we, + my_2d_array[x][y].eq(inp) + ) -f = Fragment(comb, sync) -print(verilog.convert(f)) +print(verilog.convert(Example())) diff --git a/examples/basic/complex.py b/examples/basic/complex.py index 8404cec5..d632fe44 100644 --- a/examples/basic/complex.py +++ b/examples/basic/complex.py @@ -1,16 +1,19 @@ +from migen.fhdl.module import Module from migen.genlib.complex import * from migen.fhdl import verilog -w = Complex(32, 42) -A = SignalC(16) -B = SignalC(16) -Bw = SignalC(16, variable=True) -C = SignalC(16) -D = SignalC(16) -sync = [ - Bw.eq(B*w), - C.eq(A + Bw), - D.eq(A - Bw) -] +class Example(Module): + def __init__(self): + w = Complex(32, 42) + A = SignalC(16) + B = SignalC(16) + Bw = SignalC(16, variable=True) + C = SignalC(16) + D = SignalC(16) + self.sync += [ + Bw.eq(B*w), + C.eq(A + Bw), + D.eq(A - Bw) + ] -print(verilog.convert(Fragment(sync=sync))) +print(verilog.convert(Example())) diff --git a/examples/basic/fsm.py b/examples/basic/fsm.py index 4eedd97e..5dfc4f76 100644 --- a/examples/basic/fsm.py +++ b/examples/basic/fsm.py @@ -1,9 +1,15 @@ from migen.fhdl.structure import * +from migen.fhdl.module import Module from migen.fhdl import verilog from migen.genlib.fsm import FSM -s = Signal() -myfsm = FSM("FOO", "BAR") -myfsm.act(myfsm.FOO, s.eq(1), myfsm.next_state(myfsm.BAR)) -myfsm.act(myfsm.BAR, s.eq(0), myfsm.next_state(myfsm.FOO)) -print(verilog.convert(myfsm.get_fragment(), {s})) +class Example(Module): + def __init__(self): + self.s = Signal() + myfsm = FSM("FOO", "BAR") + self.submodules += myfsm + myfsm.act(myfsm.FOO, self.s.eq(1), myfsm.next_state(myfsm.BAR)) + myfsm.act(myfsm.BAR, self.s.eq(0), myfsm.next_state(myfsm.FOO)) + +example = Example() +print(verilog.convert(example, {example.s})) diff --git a/examples/basic/lm32_inst.py b/examples/basic/lm32_inst.py deleted file mode 100644 index 1ea05a05..00000000 --- a/examples/basic/lm32_inst.py +++ /dev/null @@ -1,60 +0,0 @@ -from migen.fhdl.structure import * -from migen.fhdl.specials import Instance -from migen.bus import wishbone -from migen.fhdl import verilog - -class LM32: - def __init__(self): - self.ibus = i = wishbone.Interface() - self.dbus = d = wishbone.Interface() - self.interrupt = Signal(32) - self.ext_break = Signal() - self._i_adr_o = Signal(32) - self._d_adr_o = Signal(32) - self._inst = Instance("lm32_top", - Instance.ClockPort("clk_i"), - Instance.ResetPort("rst_i"), - - Instance.Input("interrupt", self.interrupt), - #Instance.Input("ext_break", self.ext_break), - - Instance.Output("I_ADR_O", self._i_adr_o), - Instance.Output("I_DAT_O", i.dat_w), - Instance.Output("I_SEL_O", i.sel), - Instance.Output("I_CYC_O", i.cyc), - Instance.Output("I_STB_O", i.stb), - Instance.Output("I_WE_O", i.we), - Instance.Output("I_CTI_O", i.cti), - Instance.Output("I_LOCK_O"), - Instance.Output("I_BTE_O", i.bte), - Instance.Input("I_DAT_I", i.dat_r), - Instance.Input("I_ACK_I", i.ack), - Instance.Input("I_ERR_I", i.err), - Instance.Input("I_RTY_I", 0), - - Instance.Output("D_ADR_O", self._d_adr_o), - Instance.Output("D_DAT_O", d.dat_w), - Instance.Output("D_SEL_O", d.sel), - Instance.Output("D_CYC_O", d.cyc), - Instance.Output("D_STB_O", d.stb), - Instance.Output("D_WE_O", d.we), - Instance.Output("D_CTI_O", d.cti), - Instance.Output("D_LOCK_O"), - Instance.Output("D_BTE_O", d.bte), - Instance.Input("D_DAT_I", d.dat_r), - Instance.Input("D_ACK_I", d.ack), - Instance.Input("D_ERR_I", d.err), - Instance.Input("D_RTY_I", 0)) - - def get_fragment(self): - comb = [ - self.ibus.adr.eq(self._i_adr_o[2:]), - self.dbus.adr.eq(self._d_adr_o[2:]) - ] - return Fragment(comb=comb, specials={self._inst}) - -cpus = [LM32() for i in range(4)] -frag = Fragment() -for cpu in cpus: - frag += cpu.get_fragment() -print(verilog.convert(frag, {cpus[0].interrupt})) diff --git a/examples/basic/memory.py b/examples/basic/memory.py index edfedf23..d3c8f771 100644 --- a/examples/basic/memory.py +++ b/examples/basic/memory.py @@ -1,12 +1,15 @@ from migen.fhdl.structure import Fragment from migen.fhdl.specials import Memory +from migen.fhdl.module import Module from migen.fhdl import verilog -mem = Memory(32, 100, init=[5, 18, 32]) -p1 = mem.get_port(write_capable=True, we_granularity=8) -p2 = mem.get_port(has_re=True, clock_domain="rd") +class Example(Module): + def __init__(self): + self.specials.mem = Memory(32, 100, init=[5, 18, 32]) + p1 = self.mem.get_port(write_capable=True, we_granularity=8) + p2 = self.mem.get_port(has_re=True, clock_domain="rd") + self.ios = {p1.adr, p1.dat_r, p1.we, p1.dat_w, + p2.adr, p2.dat_r, p2.re} -f = Fragment(specials={mem}) -v = verilog.convert(f, ios={p1.adr, p1.dat_r, p1.we, p1.dat_w, - p2.adr, p2.dat_r, p2.re}) -print(v) +example = Example() +print(verilog.convert(example, example.ios)) diff --git a/examples/basic/namer.py b/examples/basic/namer.py index 80f86b54..eb6c5ee2 100644 --- a/examples/basic/namer.py +++ b/examples/basic/namer.py @@ -1,5 +1,6 @@ from migen.fhdl.structure import * from migen.fhdl import verilog +from migen.fhdl.module import Module from migen.genlib.misc import optree def gen_list(n): @@ -24,17 +25,18 @@ class Toto: def __init__(self): self.sigs = gen_list(2) -a = [Bar() for x in range(3)] -b = [Foo() for x in range(3)] -c = b -b = [Bar() for x in range(2)] +class Example(Module): + def __init__(self): + a = [Bar() for x in range(3)] + b = [Foo() for x in range(3)] + c = b + b = [Bar() for x in range(2)] -output = Signal() -allsigs = [] -for lst in [a, b, c]: - for obj in lst: - allsigs.extend(obj.sigs) -comb = [output.eq(optree("|", allsigs))] + output = Signal() + allsigs = [] + for lst in [a, b, c]: + for obj in lst: + allsigs.extend(obj.sigs) + self.comb += output.eq(optree("|", allsigs)) -f = Fragment(comb) -print(verilog.convert(f)) +print(verilog.convert(Example())) diff --git a/examples/basic/psync.py b/examples/basic/psync.py index fbeb79ff..444c6274 100644 --- a/examples/basic/psync.py +++ b/examples/basic/psync.py @@ -15,6 +15,5 @@ class XilinxMultiReg: return XilinxMultiRegImpl(dr.i, dr.idomain, dr.o, dr.odomain, dr.n) ps = PulseSynchronizer("from", "to") -f = ps.get_fragment() -v = verilog.convert(f, {ps.i, ps.o}, special_overrides={MultiReg: XilinxMultiReg}) +v = verilog.convert(ps, {ps.i, ps.o}, special_overrides={MultiReg: XilinxMultiReg}) print(v) diff --git a/examples/basic/simple_gpio.py b/examples/basic/simple_gpio.py index 16d2eae8..4dc4f5fb 100644 --- a/examples/basic/simple_gpio.py +++ b/examples/basic/simple_gpio.py @@ -1,23 +1,30 @@ from migen.fhdl.structure import * +from migen.fhdl.module import Module from migen.fhdl import verilog +from migen.genlib.cdc import MultiReg from migen.bank import description, csrgen from migen.bank.description import READ_ONLY, WRITE_ONLY -ninputs = 32 -noutputs = 32 +class Example(Module): + def __init__(self, ninputs=32, noutputs=32): + r_o = description.RegisterField(noutputs, atomic_write=True) + r_i = description.RegisterField(ninputs, READ_ONLY, WRITE_ONLY) -oreg = description.RegisterField("o", noutputs, atomic_write=True) -ireg = description.RegisterField("i", ninputs, READ_ONLY, WRITE_ONLY) + self.submodules.bank = csrgen.Bank([r_o, r_i]) + self.gpio_in = Signal(ninputs) + self.gpio_out = Signal(ninputs) -# input path -gpio_in = Signal(ninputs) -gpio_in_s = Signal(ninputs) # synchronizer -insync = [gpio_in_s.eq(gpio_in), ireg.field.w.eq(gpio_in_s)] -inf = Fragment(sync=insync) + ### -bank = csrgen.Bank([oreg, ireg]) -f = bank.get_fragment() + inf -oreg.field.r.name_override = "gpio_out" -i = bank.interface -v = verilog.convert(f, {i.dat_r, oreg.field.r, i.adr, i.we, i.dat_w, gpio_in}) + gpio_in_s = Signal(ninputs) + self.specials += MultiReg(self.gpio_in, "ext", gpio_in_s, "sys") + self.comb += [ + r_i.field.w.eq(gpio_in_s), + self.gpio_out.eq(r_o.field.r) + ] + +example = Example() +i = example.bank.bus +v = verilog.convert(example, {i.dat_r, i.adr, i.we, i.dat_w, + example.gpio_in, example.gpio_out}) print(v) diff --git a/examples/basic/tristate.py b/examples/basic/tristate.py index 375524bf..b9c867d3 100644 --- a/examples/basic/tristate.py +++ b/examples/basic/tristate.py @@ -1,12 +1,16 @@ from migen.fhdl.structure import * from migen.fhdl.specials import Tristate +from migen.fhdl.module import Module from migen.fhdl import verilog -n = 6 -pad = Signal(n) -o = Signal(n) -oe = Signal() -i = Signal(n) +class Example(Module): + def __init__(self, n=6): + self.pad = Signal(n) + self.o = Signal(n) + self.oe = Signal() + self.i = Signal(n) -f = Fragment(specials={Tristate(pad, o, oe, i)}) -print(verilog.convert(f, ios={pad, o, oe, i})) + self.specials += Tristate(self.pad, self.o, self.oe, self.i) + +e = Example() +print(verilog.convert(e, ios={e.pad, e.o, e.oe, e.i})) diff --git a/examples/basic/two_dividers.py b/examples/basic/two_dividers.py index 1d15aea2..b474fa34 100644 --- a/examples/basic/two_dividers.py +++ b/examples/basic/two_dividers.py @@ -1,10 +1,15 @@ from migen.fhdl import verilog +from migen.fhdl.module import Module from migen.genlib import divider -d1 = divider.Divider(16) -d2 = divider.Divider(16) -frag = d1.get_fragment() + d2.get_fragment() -o = verilog.convert(frag, { - d1.ready_o, d1.quotient_o, d1.remainder_o, d1.start_i, d1.dividend_i, d1.divisor_i, - d2.ready_o, d2.quotient_o, d2.remainder_o, d2.start_i, d2.dividend_i, d2.divisor_i}) -print(o) +class Example(Module): + def __init__(self): + d1 = divider.Divider(16) + d2 = divider.Divider(16) + self.submodules += d1, d2 + self.ios = { + d1.ready_o, d1.quotient_o, d1.remainder_o, d1.start_i, d1.dividend_i, d1.divisor_i, + d2.ready_o, d2.quotient_o, d2.remainder_o, d2.start_i, d2.dividend_i, d2.divisor_i} + +example = Example() +print(verilog.convert(example, example.ios))