From: lkcl <lkcl@web>
Date: Mon, 5 Jun 2023 08:12:24 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9081a4da47e14c76651fef1d7dbbfab806a79ba8;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls010/trial_addi.mdwn b/openpower/sv/rfc/ls010/trial_addi.mdwn
index 049cfdf97..00812a817 100644
--- a/openpower/sv/rfc/ls010/trial_addi.mdwn
+++ b/openpower/sv/rfc/ls010/trial_addi.mdwn
@@ -44,7 +44,7 @@ but this gets massively out of hand very quickly:
 * `addi RT,RA,SI`
 
 ```
-    Defined Word-instruction:
+    Defined Word-instruction: D-Form
         |    14 |   RT            |    RA       |     SI       |
         | 0     | 6               | 11          | 16        31 |
 ```
@@ -58,11 +58,11 @@ but this gets massively out of hand very quickly:
 * `paddi RT,RA,SI,R`
 
 ```
-    Prefix:
+    Prefix: MLS
         |    1  |   2    | 0 | // | R  | //  |     si0         |
         | 0     | 6      | 8 | 9  | 11 | 12  | 14           31 |
 
-    Suffix::
+    Suffix:: D-Form
         |    14 |   RT            |    RA       | si1          |
         | 0     | 6               | 11          | 16        31 |
 ```
@@ -77,10 +77,10 @@ Operands:
 * `sv.addi RT,RA,SI`
 
 ```
-    Prefix:
+    Prefix: SVP64-RM-1S1D/EXTRA3/Normal
         |    9  |  ..    |     Stuff | EXTRA    | MODEBITS     |
         | 0     | 6      | 8         | 17    26 | 27        31 |
-    Defined Word-instruction:
+    Defined Word-instruction: D-Form
         |    14 |   RT            |    RA       |     SI       |
         | 0     | 6               | 11          | 16        31 |
 ```