From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 1 Oct 2022 21:36:04 +0000 (+0100)
Subject: replacing setvl-svstep with just svstep
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9088c34d1e40d964896615c3f903fad6bde63e1a;p=openpower-isa.git

replacing setvl-svstep with just svstep
---

diff --git a/src/openpower/decoder/isa/test_caller_svp64_fft.py b/src/openpower/decoder/isa/test_caller_svp64_fft.py
index cf5915ad..d5985755 100644
--- a/src/openpower/decoder/isa/test_caller_svp64_fft.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_fft.py
@@ -256,7 +256,7 @@ class FFTTestCase(FHDLTestCase):
                             "svshape 8, 1, 1, 1, 1",
                              "svremap 31, 1, 0, 2, 0, 1, 0",
                             "sv.ffmadds *0, *0, *0, *8",
-                            "setvl. 0, 0, 1, 1, 0, 0",
+                            "svstep. 12, 1, 0",
                             "bc 6, 3, -16"
                             ])
             runs a full in-place O(N log2 N) butterfly schedule for
@@ -271,7 +271,7 @@ class FFTTestCase(FHDLTestCase):
                         "svshape 8, 1, 1, 1, 1",
                          "svremap 31, 1, 0, 2, 0, 1, 0",
                         "sv.ffmadds *0, *0, *0, *8",
-                        "setvl. 0, 0, 1, 1, 0, 0",
+                        "svstep. 27, 1, 0",
                         "bc 6, 3, -16"
                         ])
         lst = list(lst)
@@ -343,7 +343,7 @@ class FFTTestCase(FHDLTestCase):
                          # RA: scal RB: jl (S0) RC: n/a RT: jl (S0) EA: jh (S1)
                          "svremap 26, 0, 0, 0, 0, 1, 1",
                         "sv.ffadds *0, 24, *0",
-                        "setvl. 0, 0, 1, 1, 0, 0",
+                        "svstep. 27, 1, 0",
                         "bc 6, 3, -28"
                             ])
 
@@ -382,7 +382,7 @@ class FFTTestCase(FHDLTestCase):
                          # RA: scal RB: jl (S0) RC: n/a RT: jl (S0) EA: jh (S1)
                          "svremap 26, 0, 0, 0, 0, 1, 0",
                         "sv.ffadds *0, 24, *0",
-                        "setvl. 0, 0, 1, 1, 0, 0",
+                        "svstep. 27, 1, 0",
                         "bc 6, 3, -28"
                         ])
         lst = list(lst)
@@ -616,7 +616,7 @@ class FFTTestCase(FHDLTestCase):
                         "sv.ffadds *8, 26, *8",    # vh/vl +- tpim
 
                         # svstep loop
-                        "setvl. 0, 0, 1, 1, 0, 0",
+                        "svstep. 27, 1, 0",
                         "bc 6, 3, -56"
                         ])
         lst = list(lst)