From: Robert Ou <rqou@robertou.com>
Date: Sun, 25 Jun 2017 09:20:42 +0000 (-0700)
Subject: coolrunner2: Also construct the XOR cell in the macrocell
X-Git-Tag: yosys-0.8~402^2~6
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=908ce3fdcefd095a3cb9928feb9d7dcf314d96bb;p=yosys.git

coolrunner2: Also construct the XOR cell in the macrocell
---

diff --git a/techlibs/coolrunner2/cells_sim.v b/techlibs/coolrunner2/cells_sim.v
index baeb97fa5..474d35a9a 100644
--- a/techlibs/coolrunner2/cells_sim.v
+++ b/techlibs/coolrunner2/cells_sim.v
@@ -41,3 +41,17 @@ module ORTERM(IN, OUT);
         end
     end
 endmodule
+
+module MACROCELL_XOR(IN_PTC, IN_ORTERM, OUT);
+    parameter INVERT_PTC = 0;
+    parameter INVERT_OUT = 0;
+
+    input IN_PTC;
+    input IN_ORTERM;
+    output wire OUT;
+
+    wire xor_intermed;
+
+    assign OUT = INVERT_OUT ? ~xor_intermed : xor_intermed;
+    assign xor_intermed = INVERT_PTC ? IN_ORTERM ^ ~IN_PTC : IN_ORTERM ^ IN_PTC;
+endmodule
diff --git a/techlibs/coolrunner2/coolrunner2_sop.cpp b/techlibs/coolrunner2/coolrunner2_sop.cpp
index 36bd77ad6..8ef08b43a 100644
--- a/techlibs/coolrunner2/coolrunner2_sop.cpp
+++ b/techlibs/coolrunner2/coolrunner2_sop.cpp
@@ -83,21 +83,34 @@ struct Coolrunner2SopPass : public Pass {
 						and_cell->setPort("\\IN_B", and_in_comp);
 					}
 
-					// If there is only one term, don't construct an OR cell
+					// TODO: Find the $_NOT_ on the output
+
 					if (sop_depth == 1)
 					{
-						yosys_xtrace = 1;
-						module->connect(sop_output, *intermed_wires.begin());
-						log("one\n");
+						// If there is only one term, don't construct an OR cell. Directly construct the XOR gate
+						auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR");
+						xor_cell->setParam("\\INVERT_PTC", 0);
+						xor_cell->setParam("\\INVERT_OUT", 0);
+						xor_cell->setPort("\\IN_PTC", *intermed_wires.begin());
+						xor_cell->setPort("\\OUT", sop_output);
 					}
 					else
 					{
-						log("more\n");
-						// Construct the cell
+						// Wire from OR to XOR
+						auto or_to_xor_wire = module->addWire(NEW_ID);
+
+						// Construct the OR cell
 						auto or_cell = module->addCell(NEW_ID, "\\ORTERM");
 						or_cell->setParam("\\WIDTH", sop_depth);
 						or_cell->setPort("\\IN", intermed_wires);
-						or_cell->setPort("\\OUT", sop_output);
+						or_cell->setPort("\\OUT", or_to_xor_wire);
+
+						// Construct the XOR cell
+						auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR");
+						xor_cell->setParam("\\INVERT_PTC", 0);
+						xor_cell->setParam("\\INVERT_OUT", 0);
+						xor_cell->setPort("\\IN_ORTERM", or_to_xor_wire);
+						xor_cell->setPort("\\OUT", sop_output);
 					}
 
 					// Finally, remove the $sop cell