From: Gabe Black <gblack@eecs.umich.edu>
Date: Mon, 10 Nov 2008 05:55:01 +0000 (-0800)
Subject: X86: Make the timing simple CPU handle variable length instructions.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=909380f3ee576f915f52c6245c59d41050a46f49;p=gem5.git

X86: Make the timing simple CPU handle variable length instructions.
---

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index ca1f0283e..f5eeeba60 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -561,7 +561,8 @@ TimingSimpleCPU::fetch()
 void
 TimingSimpleCPU::advanceInst(Fault fault)
 {
-    advancePC(fault);
+    if (fault != NoFault || !stayAtPC)
+        advancePC(fault);
 
     if (_status == Running) {
         // kick off fetch of next instruction... callback from icache
@@ -599,7 +600,8 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
     }
 
     preExecute();
-    if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
+    if (curStaticInst &&
+            curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
         // load or store: just send to dcache
         Fault fault = curStaticInst->initiateAcc(this, traceData);
         if (_status != Running) {
@@ -638,7 +640,7 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
                 instCnt++;
             advanceInst(fault);
         }
-    } else {
+    } else if (curStaticInst) {
         // non-memory instruction: execute completely now
         Fault fault = curStaticInst->execute(this, traceData);
 
@@ -657,6 +659,8 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
                     curStaticInst->isFirstMicroop()))
             instCnt++;
         advanceInst(fault);
+    } else {
+        advanceInst(NoFault);
     }
 
     if (pkt) {