From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 24 Jan 2015 10:03:22 +0000 (+0100)
Subject: Fixed xilinx FDSE sim model
X-Git-Tag: yosys-0.5~67
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=909a95182b6de03d6227f6331a6e60692d20203d;p=yosys.git

Fixed xilinx FDSE sim model
---

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 138a6470f..285d63dbf 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -119,8 +119,8 @@ module FDSE (output reg Q, input C, CE, D, S);
   parameter [0:0] IS_S_INVERTED = 1'b0;
   initial Q <= INIT;
   generate case (|IS_C_INVERTED)
-    1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
-    1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
+    1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
+    1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
   endcase endgenerate
 endmodule