From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 26 Apr 2021 09:32:42 +0000 (+0100)
Subject: comment read ack in sram
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=90a9100f6bf1af796d46b6ff73d1285d5daf16ba;p=soc.git

comment read ack in sram
---

diff --git a/src/soc/bus/sram.py b/src/soc/bus/sram.py
index 1575e6ae..7d634909 100644
--- a/src/soc/bus/sram.py
+++ b/src/soc/bus/sram.py
@@ -71,7 +71,9 @@ class SRAM(Elaboratable):
         if self.memory.width > len(self.bus.dat_r):
             raise NotImplementedError
 
-        # read
+        # read - this relies on the read port producing data
+        # with one clock delay. the "ack" goes out on a sync
+        # which matches that
         m.submodules.rdport = rdport = self.memory.read_port()
         m.d.comb += [
             rdport.addr.eq(self.bus.adr[:len(rdport.addr)]),