From: Claire Xenia Wolf <claire@clairexen.net>
Date: Thu, 21 Oct 2021 10:13:35 +0000 (+0200)
Subject: Fix verific.cc PRIM_DLATCH handling
X-Git-Tag: yosys-0.11~31^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=90b440f870a8ac2c91b3f716f38a4f538cad2549;p=yosys.git

Fix verific.cc PRIM_DLATCH handling

Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
---

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 6b303e4b6..18fba9b76 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -443,7 +443,13 @@ bool VerificImporter::import_netlist_instance_gates(Instance *inst, RTLIL::IdStr
 
 	if (inst->Type() == PRIM_DLATCH)
 	{
-		module->addDlatch(inst_name, net_map_at(inst->GetControl()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
+		if (inst->GetAsyncCond()->IsGnd()) {
+			module->addDlatch(inst_name, net_map_at(inst->GetControl()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
+		} else {
+			RTLIL::SigSpec sig_set = module->And(NEW_ID, net_map_at(inst->GetAsyncCond()), net_map_at(inst->GetAsyncVal()));
+			RTLIL::SigSpec sig_clr = module->And(NEW_ID, net_map_at(inst->GetAsyncCond()), module->Not(NEW_ID, net_map_at(inst->GetAsyncVal())));
+			module->addDlatchsr(inst_name, net_map_at(inst->GetControl()), sig_set, sig_clr, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
+		}
 		return true;
 	}