From: Kenneth Graunke <kenneth@whitecape.org>
Date: Fri, 5 Oct 2018 02:49:06 +0000 (-0700)
Subject: iris: stencil texturing
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=90b9efc1f97134b417db39049c8fb0bfb16078c9;p=mesa.git

iris: stencil texturing
---

diff --git a/src/gallium/drivers/iris/iris_formats.c b/src/gallium/drivers/iris/iris_formats.c
index fa77b5bcf67..0ea6be810b3 100644
--- a/src/gallium/drivers/iris/iris_formats.c
+++ b/src/gallium/drivers/iris/iris_formats.c
@@ -66,6 +66,7 @@ iris_isl_format_for_pipe_format(enum pipe_format pf)
       [PIPE_FORMAT_Z32_FLOAT_S8X24_UINT]    = ISL_FORMAT_R32_FLOAT,
 
       [PIPE_FORMAT_S8_UINT]                 = ISL_FORMAT_R8_UINT,
+      [PIPE_FORMAT_X24S8_UINT]              = ISL_FORMAT_R8_UINT,
 
       [PIPE_FORMAT_R64_FLOAT]               = ISL_FORMAT_R64_FLOAT,
       [PIPE_FORMAT_R64G64_FLOAT]            = ISL_FORMAT_R64G64_FLOAT,
diff --git a/src/gallium/drivers/iris/iris_resource.h b/src/gallium/drivers/iris/iris_resource.h
index 979e17c3e5d..6aa16c09d4c 100644
--- a/src/gallium/drivers/iris/iris_resource.h
+++ b/src/gallium/drivers/iris/iris_resource.h
@@ -64,6 +64,12 @@ struct iris_sampler_view {
    struct pipe_sampler_view base;
    struct isl_view view;
 
+   /* A short-cut (not a reference) to the actual resource being viewed.
+    * Multi-planar (or depth+stencil) images may have multiple resources
+    * chained together; this skips having to traverse base->texture->*.
+    */
+   struct iris_resource *res;
+
    /** The resource (BO) holding our SURFACE_STATE. */
    struct iris_state_ref surface_state;
 };
diff --git a/src/gallium/drivers/iris/iris_screen.c b/src/gallium/drivers/iris/iris_screen.c
index d96e2f1e117..2195128c374 100644
--- a/src/gallium/drivers/iris/iris_screen.c
+++ b/src/gallium/drivers/iris/iris_screen.c
@@ -109,7 +109,6 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
    case PIPE_CAP_DEPTH_CLIP_DISABLE:
-   case PIPE_CAP_SHADER_STENCIL_EXPORT:
    case PIPE_CAP_TGSI_INSTANCEID:
    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index b8c8c96a4ca..525bdf6a55e 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -1316,7 +1316,6 @@ iris_create_sampler_view(struct pipe_context *ctx,
 {
    struct iris_context *ice = (struct iris_context *) ctx;
    struct iris_screen *screen = (struct iris_screen *)ctx->screen;
-   struct iris_resource *itex = (struct iris_resource *) tex;
    struct iris_sampler_view *isv = calloc(1, sizeof(struct iris_sampler_view));
 
    if (!isv)
@@ -1337,6 +1336,18 @@ iris_create_sampler_view(struct pipe_context *ctx,
    struct iris_bo *state_bo = iris_resource_bo(isv->surface_state.res);
    isv->surface_state.offset += iris_bo_offset_from_base_address(state_bo);
 
+   if (util_format_is_depth_or_stencil(tmpl->format)) {
+      struct iris_resource *zres, *sres;
+      const struct util_format_description *desc =
+         util_format_description(tmpl->format);
+
+      iris_get_depth_stencil_resources(tex, &zres, &sres);
+
+      tex = util_format_has_depth(desc) ? &zres->base : &sres->base;
+   }
+
+   isv->res = (struct iris_resource *) tex;
+
    /* XXX: do we need brw_get_texture_swizzle hacks here? */
    isv->view = (struct isl_view) {
       .format = iris_isl_format_for_pipe_format(tmpl->format),
@@ -1347,7 +1358,7 @@ iris_create_sampler_view(struct pipe_context *ctx,
          .a = pipe_swizzle_to_isl_channel(tmpl->swizzle_a),
       },
       .usage = ISL_SURF_USAGE_TEXTURE_BIT |
-               (itex->surf.usage & ISL_SURF_USAGE_CUBE_BIT),
+               (isv->res->surf.usage & ISL_SURF_USAGE_CUBE_BIT),
    };
 
    /* Fill out SURFACE_STATE for this view. */
@@ -1359,9 +1370,9 @@ iris_create_sampler_view(struct pipe_context *ctx,
          tmpl->u.tex.last_layer - tmpl->u.tex.first_layer + 1;
 
       isl_surf_fill_state(&screen->isl_dev, map,
-                          .surf = &itex->surf, .view = &isv->view,
+                          .surf = &isv->res->surf, .view = &isv->view,
                           .mocs = MOCS_WB,
-                          .address = itex->bo->gtt_offset);
+                          .address = isv->res->bo->gtt_offset);
                           // .aux_surf =
                           // .clear_color = clear_color,
    } else {
@@ -1371,7 +1382,7 @@ iris_create_sampler_view(struct pipe_context *ctx,
       const unsigned cpp = fmtl->bpb / 8;
 
       isl_buffer_fill_state(&screen->isl_dev, map,
-                            .address = itex->bo->gtt_offset +
+                            .address = isv->res->bo->gtt_offset +
                                        tmpl->u.buf.offset,
                             // XXX: buffer_texture_range_size from i965?
                             .size_B = tmpl->u.buf.size,
@@ -3099,7 +3110,7 @@ use_surface(struct iris_batch *batch,
 static uint32_t
 use_sampler_view(struct iris_batch *batch, struct iris_sampler_view *isv)
 {
-   iris_use_pinned_bo(batch, iris_resource_bo(isv->base.texture), false);
+   iris_use_pinned_bo(batch, isv->res->bo, false);
    iris_use_pinned_bo(batch, iris_resource_bo(isv->surface_state.res), false);
 
    return isv->surface_state.offset;