From: Kaj Tuomi <kaj.tuomi@siru.fi>
Date: Thu, 12 Oct 2017 10:05:10 +0000 (+0300)
Subject: Fix input vector for reduce cells.
X-Git-Tag: yosys-0.8~296^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=90be0d8;p=yosys.git

Fix input vector for reduce cells.
---

diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index eb9d02ad5..10bdf7221 100644
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -88,6 +88,7 @@ struct OptReduceWorker
 		RTLIL::SigSpec new_sig_a(new_sig_a_bits);
 
 		if (new_sig_a != sig_a || sig_a.size() != cell->getPort("\\A").size()) {
+			new_sig_a.sort_and_unify();
 			log("    New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
 			did_something = true;
 			total_count++;