From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 3 Nov 2018 08:02:17 +0000 (+0000)
Subject: add some twin-predication zeroing unit tests on c.mv
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=90da209c49050e8301d487b08609b43aff47ab84;p=riscv-tests.git

add some twin-predication zeroing unit tests on c.mv
---

diff --git a/isa/rv64uc/sv_c_mv_predication.S b/isa/rv64uc/sv_c_mv_predication.S
index 7345de0..76d744c 100644
--- a/isa/rv64uc/sv_c_mv_predication.S
+++ b/isa/rv64uc/sv_c_mv_predication.S
@@ -4,7 +4,8 @@
 RVTEST_RV64U        # Define TVM used by program.
 
 
-#define SV_PRED_C_MV_TEST( pred1, pred2, expect1, expect2, expect3 ) \
+#define SV_PRED_C_MV_TEST( pred1, pred2, zero1, zero2, \
+                            expect1, expect2, expect3 ) \
                                                        \
         SV_LD_DATA( x6, testdata+0 , 0);               \
         SV_LD_DATA( x7, testdata+8, 0);                \
@@ -20,8 +21,8 @@ RVTEST_RV64U        # Define TVM used by program.
         SET_SV_2CSRS( SV_REG_CSR(1, 3, 0, 3, 1),       \
                       SV_REG_CSR(1, 6, 0, 6, 1) );     \
         SET_SV_2PREDCSRS(                              \
-                      SV_PRED_CSR(1, 3, 0, 0, 13, 0),  \
-                      SV_PRED_CSR(1, 6, 0, 0, 14, 0) );\
+                      SV_PRED_CSR(1, 3, zero1, 0, 13, 0),  \
+                      SV_PRED_CSR(1, 6, zero2, 0, 14, 0) );\
         SET_SV_VL(3);                                  \
                                                        \
         .option rvc;                                   \
@@ -46,24 +47,32 @@ RVTEST_CODE_BEGIN   # Start of test code.
 
         .option norvc
 
-        SV_PRED_C_MV_TEST( 0x7, 0x7, 1001, 41, 42 )
-        SV_PRED_C_MV_TEST( 0x3, 0x7, 1001, 41, 4 )
-        SV_PRED_C_MV_TEST( 0x1, 0x7, 1001, 3, 4 )
+        SV_PRED_C_MV_TEST( 0x7, 0x7, 0, 0, 1001, 41, 42 )
+        SV_PRED_C_MV_TEST( 0x3, 0x7, 0, 0, 1001, 41, 4 )
+        SV_PRED_C_MV_TEST( 0x1, 0x7, 0, 0, 1001, 3, 4 )
 
-        SV_PRED_C_MV_TEST( 0x6, 0x7, 2, 1001, 41 )
-        SV_PRED_C_MV_TEST( 0x6, 0x3, 2, 1001, 41 )
-        SV_PRED_C_MV_TEST( 0x6, 0x1, 2, 1001, 4 )
-        SV_PRED_C_MV_TEST( 0x6, 0x6, 2, 41, 42 )
+        SV_PRED_C_MV_TEST( 0x6, 0x7, 0, 0, 2, 1001, 41 )
+        SV_PRED_C_MV_TEST( 0x6, 0x3, 0, 0, 2, 1001, 41 )
+        SV_PRED_C_MV_TEST( 0x6, 0x1, 0, 0, 2, 1001, 4 )
+        SV_PRED_C_MV_TEST( 0x6, 0x6, 0, 0, 2, 41, 42 )
 
-        SV_PRED_C_MV_TEST( 0x5, 0x6, 41, 3, 42 )
+        SV_PRED_C_MV_TEST( 0x5, 0x6, 0, 0, 41, 3, 42 )
 
-        SV_PRED_C_MV_TEST( 0x1, 0x1, 1001, 3, 4 )
-        SV_PRED_C_MV_TEST( 0x2, 0x1, 2, 1001, 4 )
-        SV_PRED_C_MV_TEST( 0x4, 0x1, 2, 3, 1001 )
+        SV_PRED_C_MV_TEST( 0x1, 0x1, 0, 0, 1001, 3, 4 )
+        SV_PRED_C_MV_TEST( 0x2, 0x1, 0, 0, 2, 1001, 4 )
+        SV_PRED_C_MV_TEST( 0x4, 0x1, 0, 0, 2, 3, 1001 )
 
-        SV_PRED_C_MV_TEST( 0x1, 0x1, 1001, 3, 4 )
-        SV_PRED_C_MV_TEST( 0x1, 0x2, 41, 3, 4 )
-        SV_PRED_C_MV_TEST( 0x1, 0x4, 42, 3, 4 )
+        SV_PRED_C_MV_TEST( 0x1, 0x1, 0, 0, 1001, 3, 4 )
+        SV_PRED_C_MV_TEST( 0x1, 0x2, 0, 0, 41, 3, 4 )
+        SV_PRED_C_MV_TEST( 0x1, 0x4, 0, 0, 42, 3, 4 )
+
+        # test zeroing with predication
+        SV_PRED_C_MV_TEST( 0x1, 0x1, 1, 1, 1001, 0, 0 )
+        SV_PRED_C_MV_TEST( 0x2, 0x3, 1, 1, 0, 41, 0 )
+        SV_PRED_C_MV_TEST( 0x5, 0x5, 1, 1, 1001, 0, 42 )
+        SV_PRED_C_MV_TEST( 0x1, 0x1, 1, 0, 1001, 3, 4 )
+        SV_PRED_C_MV_TEST( 0x2, 0x3, 1, 0, 0, 41, 4 )
+        SV_PRED_C_MV_TEST( 0x5, 0x5, 1, 0, 1001, 0, 4 )
 
         RVTEST_PASS           # Signal success.
 fail: