From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 24 May 2020 11:54:55 +0000 (+0100)
Subject: TODO mention OP_MTMSR/OP_MFMSR
X-Git-Tag: div_pipeline~892
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=90dc44ba581757e7ae0dc7a67f2e629fef7f1627;p=soc.git

TODO mention OP_MTMSR/OP_MFMSR
---

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index 690f60c0..105060c7 100644
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -1,3 +1,7 @@
+"""Trap Pipeline
+
+* https://bugs.libre-soc.org/show_bug.cgi?id=325
+"""
 
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, signed)
 from nmutil.pipemodbase import PipeModBase
@@ -83,6 +87,9 @@ class TrapMainStage(PipeModBase):
                     comb += self.o.srr0.data.eq(self.i.cia)   # old PC
                     comb += self.o.srr0.ok.eq(1)
 
+            # XXX TODO, needs the lines adding to the CSV files first
+            #with m.Case(InternalOp.OP_MTMSR):
+            #with m.Case(InternalOp.OP_MFMSR):
         comb += self.o.ctx.eq(self.i.ctx)
 
         return m