From: Ron Dreslinski Date: Wed, 15 Feb 2006 19:53:02 +0000 (-0500) Subject: Changes to start making the tree use the new memory system. Trying to compile decode... X-Git-Tag: m5_2.0_beta1~234 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=90def9ea9ee17c63af846685d55d8956b37476ab;p=gem5.git Changes to start making the tree use the new memory system. Trying to compile decoder.cc but fails still. SConscript: Place the memory objects back in the right place arch/alpha/isa_desc: Fix includes to point to the new memory requests cpu/exec_context.hh: Exec context now points to memory object, fix the include paths. Convert to prot_read/prot_write functions instead of read and write. Convert to new CpuRequestPtr instead of MemReqPtr. mem/request.hh: Add back in support for Request Flags (needed by decoder to tag request) Removed the flags that were associated with packets/coherence. sim/process.hh: Converted to point to new memory objects --HG-- extra : convert_revision : a0b95380915d63b53194e2a26336d6adb1a0086b --- diff --git a/SConscript b/SConscript index c5851675f..987eccceb 100644 --- a/SConscript +++ b/SConscript @@ -44,11 +44,6 @@ Import('env') # Base sources used by all configurations. base_sources = Split(''' - mem/memory.cc - mem/page_table.cc - mem/physical.cc - mem/proxy.cc - arch/alpha/decoder.cc arch/alpha/alpha_o3_exec.cc arch/alpha/fast_cpu_exec.cc @@ -131,6 +126,11 @@ base_sources = Split(''' encumbered/mem/functional/main.cc + mem/memory.cc + mem/page_table.cc + mem/physical.cc + mem/proxy.cc + python/pyconfig.cc python/embedded_py.cc diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index c998b1a0a..e64a95957 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -47,7 +47,7 @@ output header {{ #include "config/ss_compatible_fp.hh" #include "cpu/static_inst.hh" -#include "mem/mem_req.hh" // some constructors use MemReq flags +#include "mem/request.hh" // some constructors use MemReq flags }}; output decoder {{ diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh index 70d731517..8ab3506db 100644 --- a/cpu/exec_context.hh +++ b/cpu/exec_context.hh @@ -30,14 +30,13 @@ #define __CPU_EXEC_CONTEXT_HH__ #include "config/full_system.hh" -#include "mem/functional/functional.hh" -#include "mem/mem_interface.hh" -#include "mem/mem_req.hh" +#include "mem/physical.hh" +#include "mem/request.hh" #include "sim/host.hh" #include "sim/serialize.hh" #include "targetarch/byte_swap.hh" -class PhysicalMemory; +class Memory; class BaseCPU; #if FULL_SYSTEM @@ -123,7 +122,7 @@ class ExecContext int cpu_id; System *system; - FunctionalMemory *mem; + Memory *mem; #if FULL_SYSTEM AlphaITB *itb; @@ -133,7 +132,7 @@ class ExecContext // look them up through the system pointer, but we'll leave them // here for now for convenience MemoryController *memctrl; - PhysicalMemory *physmem; +// PhysicalMemory *physmem; Kernel::Binning *kernelBinning; Kernel::Statistics *kernelStats; @@ -185,7 +184,7 @@ class ExecContext AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem); #else ExecContext(BaseCPU *_cpu, int _thread_num, System *_system, - FunctionalMemory *_mem, Process *_process, int _asid); + Memory *_mem, Process *_process, int _asid); #endif virtual ~ExecContext(); @@ -202,17 +201,17 @@ class ExecContext int getInstAsid() { return regs.instAsid(); } int getDataAsid() { return regs.dataAsid(); } - Fault translateInstReq(MemReqPtr &req) + Fault translateInstReq(CpuRequestPtr &req) { return itb->translate(req); } - Fault translateDataReadReq(MemReqPtr &req) + Fault translateDataReadReq(CpuRequestPtr &req) { return dtb->translate(req, false); } - Fault translateDataWriteReq(MemReqPtr &req) + Fault translateDataWriteReq(CpuRequestPtr &req) { return dtb->translate(req, true); } @@ -227,17 +226,17 @@ class ExecContext int getInstAsid() { return asid; } int getDataAsid() { return asid; } - Fault translateInstReq(MemReqPtr &req) + Fault translateInstReq(CpuRequestPtr &req) { return process->pTable->translate(req); } - Fault translateDataReadReq(MemReqPtr &req) + Fault translateDataReadReq(CpuRequestPtr &req) { return process->pTable->translate(req); } - Fault translateDataWriteReq(MemReqPtr &req) + Fault translateDataWriteReq(CpuRequestPtr &req) { return process->pTable->translate(req); } @@ -245,7 +244,7 @@ class ExecContext #endif template - Fault read(MemReqPtr &req, T &data) + Fault read(CpuRequestPtr &req, T &data) { #if FULL_SYSTEM && defined(TARGET_ALPHA) if (req->flags & LOCKED) { @@ -256,13 +255,13 @@ class ExecContext #endif Fault error; - error = mem->read(req, data); + error = mem->prot_read(req->paddr, data, req->size); data = gtoh(data); return error; } template - Fault write(MemReqPtr &req, T &data) + Fault write(CpuRequestPtr &req, T &data) { #if FULL_SYSTEM && defined(TARGET_ALPHA) @@ -307,7 +306,7 @@ class ExecContext } #endif - return mem->write(req, (T)htog(data)); + return mem->prot_write(req->paddr, (T)htog(data), req->size); } virtual bool misspeculating(); @@ -320,7 +319,7 @@ class ExecContext inst = new_inst; } - Fault instRead(MemReqPtr &req) + Fault instRead(CpuRequestPtr &req) { panic("instRead not implemented"); // return funcPhysMem->read(req, inst); diff --git a/mem/request.hh b/mem/request.hh index 9f03c4e75..24296f1df 100644 --- a/mem/request.hh +++ b/mem/request.hh @@ -42,6 +42,19 @@ class CpuRequest; typedef Request* RequestPtr; typedef CpuRequest* CpuRequestPtr; +/** The request is a Load locked/store conditional. */ +const unsigned LOCKED = 0x001; +/** The virtual address is also the physical address. */ +const unsigned PHYSICAL = 0x002; +/** The request is an ALPHA VPTE pal access (hw_ld). */ +const unsigned VPTE = 0x004; +/** Use the alternate mode bits in ALPHA. */ +const unsigned ALTMODE = 0x008; +/** The request is to an uncacheable address. */ +const unsigned UNCACHEABLE = 0x010; +/** The request should not cause a page fault. */ +const unsigned NO_FAULT = 0x020; + class Request { //@todo Make Accesor functions, make these private. @@ -60,6 +73,8 @@ class Request /** Destination address if this is a block copy. */ Addr copyDest; + + uint32_t flags; }; class CpuRequest : public Request diff --git a/sim/process.hh b/sim/process.hh index e7e0b8a9b..cdd28982d 100644 --- a/sim/process.hh +++ b/sim/process.hh @@ -42,15 +42,15 @@ #include "base/statistics.hh" #include "base/trace.hh" -#include "mem/base_mem.hh" -#include "mem/mem_interface.hh" +#include "mem/memory.hh" +//#include "mem/mem_interface.hh" #include "mem/page_table.hh" #include "sim/sim_object.hh" #include "sim/stats.hh" #include "targetarch/isa_traits.hh" class ExecContext; -class FunctionalMemory; +class Memory; class System; class Process : public SimObject @@ -128,7 +128,7 @@ class Process : public SimObject protected: /// Memory object for initialization (image loading) - FunctionalMemory *initVirtMem; + Memory *initVirtMem; public: PageTable *pTable;