From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 13 Oct 2018 13:43:06 +0000 (+0100)
Subject: rename _zext_xlen
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=90e547f98f72245d87419a1c2dbd9722ab43aeb4;p=riscv-isa-sim.git

rename _zext_xlen
---

diff --git a/riscv/decode.h b/riscv/decode.h
index f7a8f10..2257327 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -198,12 +198,16 @@ private:
 
 #define sext32(x) ((sreg_t)(int32_t)(x))
 #define zext32(x) ((reg_t)(uint32_t)(x))
+
+#define _sext_xlen(x) (((sreg_t)(x) << (64-xlen)) >> (64-xlen))
 #define sext_xlen(x) (((sreg_t)(x) << (64-xlen)) >> (64-xlen))
+
+#define _zext_xlen(x) (((reg_t)(x) << (64-xlen)) >> (64-xlen))
 #define zext_xlen(x) (((reg_t)(x) << (64-xlen)) >> (64-xlen))
 
 #define _set_pc(x) \
   do { p->check_pc_alignment(x); \
-       npc = sext_xlen(x); \
+       npc = _sext_xlen(x); \
      } while(0)
 
 #ifndef SPIKE_SIMPLEV
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 0b6dcfa..9aa17a8 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -335,7 +335,7 @@ int processor_t::paddr_bits()
 
 void processor_t::set_csr(int which, reg_t val)
 {
-  val = zext_xlen(val);
+  val = _zext_xlen(val);
   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP
                        | ((ext != NULL) << IRQ_COP);
   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;