From: lkcl <lkcl@web>
Date: Thu, 29 Sep 2022 22:50:20 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~259
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=90f1ebaf69baf373a0f821aa32bcb4fa0c0f10ea;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 09cdb52dc..a73c0c8ce 100644
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -174,9 +174,7 @@ such large numbers of registers, even for Multi-Issue microarchitectures.
 * A third 24-bits (third 2-bit XO) is strongly recommended to be `RESERVED`
   such that future unforeseen capability is needed (although this may be
   alternatively achieved with a mandatory PCR or MSR bit)
-* To hold all Vector Context, five SPRs are needed for userspace.
-  If Supervisor and Hypervisor mode are to
-  also support Simple-V they will correspondingly need five SPRs each.
+* To hold all Vector Context, four SPRs are needed.
   (Some 32/32-to-64 aliases are advantageous but not critical).
 * Five 6-bit XO (A-Form) "Management" instructions are needed.  These are
   Scalar 32-bit instructions and *may* be 64-bit-extended in future
@@ -196,8 +194,6 @@ at least the next decade (including if added on VSX)
   Context-switching and no adverse latency, it may be considered to
   be a "Sub-PC" and as such absolutely must be treated with the same
   respect and priority as MSR and PC.
-* **SVSRR0** - identical in purpose to SRR0/1: storing SVSTATE on context-switch
-  along-side MSR and PC.
 * **SVSHAPE0-3** - these are 32-bit and may be grouped in pairs, they REMAP
   (shape) the Vectors[^svshape]
 * **SVLR** - again similar to LR for exactly the same purpose, SVSTATE