From: lkcl <lkcl@web>
Date: Thu, 8 Sep 2022 11:52:48 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~638
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=90fec6500de757f2dc5f1c0ba70be1d17f310418;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 26e68033d..1db110afd 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -138,7 +138,7 @@ Pages being developed and examples
   or are not immediately apparent despite the RISC paradigm
 * [[opcode_regs_deduped]] autogenerated table of SVP64 decoder augmentation
 * [[sv/sprs]] SPRs
-* [[sv/rfc]] RFCs to the [OPF ISA WG]()
+* [[sv/rfc]] RFCs to the [OPF ISA WG](https://openpower.foundation/isarfc/)
 
 SVP64 "Modes":