From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 5 Dec 2021 20:48:35 +0000 (+0000)
Subject: split out TLBRecord, correct number of valid bits
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=90ff9cea03908b86732639a1cc092cd67341442a;p=soc.git

split out TLBRecord, correct number of valid bits
---

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index d477d340..d337ffc8 100644
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -195,13 +195,19 @@ def TLBTagEAArray():
     return Array(Signal(TLB_EA_TAG_BITS, name="tlbtagea%d" % x) \
                 for x in range (TLB_NUM_WAYS))
 
-def TLBArray():
+def TLBRecord(name):
     tlb_layout = [('valid', 1),
                   ('tag', TLB_TAG_WAY_BITS),
                   ('pte', TLB_PTE_WAY_BITS)
                  ]
-    return Array(Record(tlb_layout, name="tlb%d" % x) \
-                        for x in range(TLB_SET_SIZE))
+    return Record(tlb_layout, name=name)
+
+def TLBArray():
+    tlb_layout = [('valid', TLB_NUM_WAYS),
+                  ('tag', TLB_TAG_WAY_BITS),
+                  ('pte', TLB_PTE_WAY_BITS)
+                 ]
+    return Array(TLBRecord(name="tlb%d" % x) for x in range(TLB_SET_SIZE))
 
 def HitWaySet():
     return Array(Signal(WAY_BITS, name="hitway_%d" % x) \