From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 11 Jul 2019 05:25:52 +0000 (+0200)
Subject: Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmark
X-Git-Tag: working-ls180~1205
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9112850800a92ed0e330d8470e1273116d78ba14;p=yosys.git

Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmark

write_verilog: write RTLIL::Sa aka - as Verilog ?
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9112850800a92ed0e330d8470e1273116d78ba14