From: Luke Kenneth Casson Leighton Date: Wed, 2 Jun 2021 13:34:52 +0000 (+0100) Subject: found FP single-conversion error, from the pseudocode, incorrectly X-Git-Tag: xlen-bcd~487 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=911645bdd72f91908cd298b2789ef2eb468a791b;p=openpower-isa.git found FP single-conversion error, from the pseudocode, incorrectly translated to python by hand. really should replace it with actual pseudocode --- diff --git a/src/openpower/decoder/helpers.py b/src/openpower/decoder/helpers.py index 7e83faef..db7ef6da 100644 --- a/src/openpower/decoder/helpers.py +++ b/src/openpower/decoder/helpers.py @@ -174,22 +174,22 @@ def DOUBLE(WORD): FRT[4] = ~WORD[1] FRT[5:64] = selectconcat(WORD[2:32], z29) - # Denormalized Operand - if e.value == 0 and m.value != 0: - log ("denormalised") - sign = WORD[0] - exp = -126 - frac = selectconcat(z1, WORD[9:32], z29) - # normalize the operand - while frac[0].value == 0: - frac[0:53] = selectconcat(frac[1:53], z1) - exp = exp - 1 - FRT[0] = sign - FRT[1:12] = exp + 1023 - FRT[12:64] = frac[1:53] + # Denormalized Operand + if e.value == 0 and m.value != 0: + log ("denormalised") + sign = WORD[0] + exp = -126 + frac = selectconcat(z1, WORD[9:32], z29) + # normalize the operand + while frac[0].value == 0: + frac[0:53] = selectconcat(frac[1:53], z1) + exp = exp - 1 + FRT[0] = sign + FRT[1:12] = exp + 1023 + FRT[12:64] = frac[1:53] # Zero / Infinity / NaN - if e.value == 255 or m.value == 0: + if e.value == 255 or WORD[1:32].value == 0: log ("z/inf/nan") FRT[0:2] = WORD[0:2] FRT[2] = WORD[1] diff --git a/src/openpower/decoder/isa/test_caller_fp.py b/src/openpower/decoder/isa/test_caller_fp.py index 3d8fdfa9..5e745ef4 100644 --- a/src/openpower/decoder/isa/test_caller_fp.py +++ b/src/openpower/decoder/isa/test_caller_fp.py @@ -38,6 +38,21 @@ class DecoderTestCase(FHDLTestCase): print("FPR 1", sim.fpr(1)) self.assertEqual(sim.fpr(1), SelectableInt(0x4040266660000000, 64)) + def test_fpload2(self): + """>>> lst = ["lfsx 1, 0, 0", + ] + """ + lst = ["lfsx 1, 0, 0", + ] + initial_mem = {0x0000: (0xac000000, 8), + 0x0020: (0x1828384822324252, 8), + } + + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, initial_mem=initial_mem) + print("FPR 1", sim.fpr(1)) + self.assertEqual(sim.fpr(1), SelectableInt(0xbd80000000000000, 64)) + def test_fp_single_ldst(self): """>>> lst = ["lfsx 1, 1, 0", # load fp 1 from mem location 0 "stfsu 1, 16(1)", # store fp 1 into mem 0x10, update RA