From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 22 Nov 2019 00:13:28 +0000 (-0800)
Subject: Add test
X-Git-Tag: working-ls180~881^2^2~161
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=911a152b39959137b26e68581a6cacbcabb4ab1d;p=yosys.git

Add test
---

diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index 1844bac20..13c505eec 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -268,7 +268,12 @@ assign o = { 1'b1, 1'bx };
 assign p = { 1'b1, 1'bx, 1'b0 };
 endmodule
 
-module abc9_test029(input clk1, clk2, input d, output reg q1, q2);
+module abc9_test029(input clk1, clk2, d, output reg q1, q2);
 always @(posedge clk1) q1 <= d;
 always @(negedge clk2) q2 <= q1;
 endmodule
+
+module abc9_test030(input clk, d, output reg q1, q2);
+always @(posedge clk) q1 <= d;
+always @(posedge clk) q2 <= q1;
+endmodule