From: Luke Kenneth Casson Leighton Date: Mon, 28 Sep 2020 11:27:34 +0000 (+0100) Subject: add "nocore" option to build verilog X-Git-Tag: 24jan2021_ls180~295 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=911b4858ff2fb8cf605bc0b530269182f7a6f5a9;p=soc.git add "nocore" option to build verilog --- diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index 356e6198..7fa96c0a 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -120,6 +120,9 @@ class NonProductionCore(Elaboratable): def elaborate(self, platform): m = Module() + # for testing purposes, to cut down on build time in coriolis2 + if hasattr(self.pspec, "nocore") and self.pspec.nocore == True: + return m comb = m.d.comb m.submodules.fus = self.fus diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py index 820e5fd3..eec494af 100644 --- a/src/soc/simple/issuer_verilog.py +++ b/src/soc/simple/issuer_verilog.py @@ -28,6 +28,7 @@ if __name__ == '__main__': # set to 32 to make data wishbone bus 32-bit #wb_data_wid=32, xics=True, + nocore=True, # to help test coriolis2 ioring gpio=False, # for test purposes debug="jtag", # set to jtag or dmi units=units)