From: Luke Kenneth Casson Leighton Date: Wed, 3 Jun 2020 01:28:59 +0000 (+0100) Subject: Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] microwatt decoder tables: M-Form and... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=912d7a7890453bc0c9a2ec7887e51950fbff3fb1;p=libre-riscv-dev.git Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] microwatt decoder tables: M-Form and X-Form switched RS and RB --- diff --git a/9e/f97e9de23dc8ce1b5c808909de387f90ce2bce b/9e/f97e9de23dc8ce1b5c808909de387f90ce2bce new file mode 100644 index 0000000..fa13456 --- /dev/null +++ b/9e/f97e9de23dc8ce1b5c808909de387f90ce2bce @@ -0,0 +1,129 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Wed, 03 Jun 2020 02:29:35 +0100 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-soc.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jgIDm-0000kY-A7; Wed, 03 Jun 2020 02:29:34 +0100 +Received: from lkcl.net ([217.147.94.29]) + by libre-soc.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) + (Exim 4.89) (envelope-from ) id 1jgIDl-0000kS-E3 + for libre-riscv-dev@lists.libre-riscv.org; Wed, 03 Jun 2020 02:29:33 +0100 +DKIM-Signature: v=1; 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