From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 5 Jun 2021 11:09:54 +0000 (+0000)
Subject: add coresync_clk to list of HTree
X-Git-Tag: LS180_RC3~27^2~10
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=913ad2a5a9145b15284fb7899d3aad90dd7a005a;p=soclayout.git

add coresync_clk to list of HTree
---

diff --git a/experiments10_verilog/doDesign.py b/experiments10_verilog/doDesign.py
index f7ee17d..74a5be1 100644
--- a/experiments10_verilog/doDesign.py
+++ b/experiments10_verilog/doDesign.py
@@ -85,6 +85,7 @@ def scriptMain ( **kw ):
         adderConf.chipConf.name = 'chip'
         #adderConf.chipConf.ioPadGauge = 'LibreSOCIO'
         adderConf.chipConf.ioPadGauge = 'niolib'
+        adderConf.useHTree('coresync_clk')
         adderConf.useHTree('jtag_tck_from_pad')
         adderConf.useHTree('sys_clk_from_pad')
         adderConf.coreSize = ( l(coreSize), l(coreSize) )