From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 28 May 2019 16:35:45 +0000 (-0700)
Subject: Update from master
X-Git-Tag: working-ls180~1208^2~253
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=914074a07c14709523cc72084e1673bd3c2eaf30;p=yosys.git

Update from master
---

diff --git a/backends/json/json.cc b/backends/json/json.cc
index b4f82a3fe..f5c687981 100644
--- a/backends/json/json.cc
+++ b/backends/json/json.cc
@@ -130,75 +130,72 @@ struct JsonWriter
 			f << stringf("        }");
 			first = false;
 		}
-		f << stringf("\n      }");
+		f << stringf("\n      },\n");
 
-		if (!module->get_blackbox_attribute()) {
-			f << stringf(",\n      \"cells\": {");
-			first = true;
-			for (auto c : module->cells()) {
-				if (use_selection && !module->selected(c))
-					continue;
-				f << stringf("%s\n", first ? "" : ",");
-				f << stringf("        %s: {\n", get_name(c->name).c_str());
-				f << stringf("          \"hide_name\": %s,\n", c->name[0] == '$' ? "1" : "0");
-				f << stringf("          \"type\": %s,\n", get_name(c->type).c_str());
-				if (aig_mode) {
-					Aig aig(c);
-					if (!aig.name.empty()) {
-						f << stringf("          \"model\": \"%s\",\n", aig.name.c_str());
-						aig_models.insert(aig);
-					}
-				}
-				f << stringf("          \"parameters\": {");
-				write_parameters(c->parameters);
-				f << stringf("\n          },\n");
-				f << stringf("          \"attributes\": {");
-				write_parameters(c->attributes);
-				f << stringf("\n          },\n");
-				if (c->known()) {
-					f << stringf("          \"port_directions\": {");
-					bool first2 = true;
-					for (auto &conn : c->connections()) {
-						string direction = "output";
-						if (c->input(conn.first))
-							direction = c->output(conn.first) ? "inout" : "input";
-						f << stringf("%s\n", first2 ? "" : ",");
-						f << stringf("            %s: \"%s\"", get_name(conn.first).c_str(), direction.c_str());
-						first2 = false;
-					}
-					f << stringf("\n          },\n");
+		f << stringf("      \"cells\": {");
+		first = true;
+		for (auto c : module->cells()) {
+			if (use_selection && !module->selected(c))
+				continue;
+			f << stringf("%s\n", first ? "" : ",");
+			f << stringf("        %s: {\n", get_name(c->name).c_str());
+			f << stringf("          \"hide_name\": %s,\n", c->name[0] == '$' ? "1" : "0");
+			f << stringf("          \"type\": %s,\n", get_name(c->type).c_str());
+			if (aig_mode) {
+				Aig aig(c);
+				if (!aig.name.empty()) {
+					f << stringf("          \"model\": \"%s\",\n", aig.name.c_str());
+					aig_models.insert(aig);
 				}
-				f << stringf("          \"connections\": {");
+			}
+			f << stringf("          \"parameters\": {");
+			write_parameters(c->parameters);
+			f << stringf("\n          },\n");
+			f << stringf("          \"attributes\": {");
+			write_parameters(c->attributes);
+			f << stringf("\n          },\n");
+			if (c->known()) {
+				f << stringf("          \"port_directions\": {");
 				bool first2 = true;
 				for (auto &conn : c->connections()) {
+					string direction = "output";
+					if (c->input(conn.first))
+						direction = c->output(conn.first) ? "inout" : "input";
 					f << stringf("%s\n", first2 ? "" : ",");
-					f << stringf("            %s: %s", get_name(conn.first).c_str(), get_bits(conn.second).c_str());
+					f << stringf("            %s: \"%s\"", get_name(conn.first).c_str(), direction.c_str());
 					first2 = false;
 				}
-				f << stringf("\n          }\n");
-				f << stringf("        }");
-				first = false;
+				f << stringf("\n          },\n");
 			}
-			f << stringf("\n      },\n");
-
-			f << stringf("      \"netnames\": {");
-			first = true;
-			for (auto w : module->wires()) {
-				if (use_selection && !module->selected(w))
-					continue;
-				f << stringf("%s\n", first ? "" : ",");
-				f << stringf("        %s: {\n", get_name(w->name).c_str());
-				f << stringf("          \"hide_name\": %s,\n", w->name[0] == '$' ? "1" : "0");
-				f << stringf("          \"bits\": %s,\n", get_bits(w).c_str());
-				f << stringf("          \"attributes\": {");
-				write_parameters(w->attributes);
-				f << stringf("\n          }\n");
-				f << stringf("        }");
-				first = false;
+			f << stringf("          \"connections\": {");
+			bool first2 = true;
+			for (auto &conn : c->connections()) {
+				f << stringf("%s\n", first2 ? "" : ",");
+				f << stringf("            %s: %s", get_name(conn.first).c_str(), get_bits(conn.second).c_str());
+				first2 = false;
 			}
-			f << stringf("\n      }");
+			f << stringf("\n          }\n");
+			f << stringf("        }");
+			first = false;
+		}
+		f << stringf("\n      },\n");
+
+		f << stringf("      \"netnames\": {");
+		first = true;
+		for (auto w : module->wires()) {
+			if (use_selection && !module->selected(w))
+				continue;
+			f << stringf("%s\n", first ? "" : ",");
+			f << stringf("        %s: {\n", get_name(w->name).c_str());
+			f << stringf("          \"hide_name\": %s,\n", w->name[0] == '$' ? "1" : "0");
+			f << stringf("          \"bits\": %s,\n", get_bits(w).c_str());
+			f << stringf("          \"attributes\": {");
+			write_parameters(w->attributes);
+			f << stringf("\n          }\n");
+			f << stringf("        }");
+			first = false;
 		}
-		f << stringf("\n");
+		f << stringf("\n      }\n");
 
 		f << stringf("    }");
 	}
diff --git a/kernel/cellaigs.cc b/kernel/cellaigs.cc
index 5fd76afe5..26c625f89 100644
--- a/kernel/cellaigs.cc
+++ b/kernel/cellaigs.cc
@@ -453,7 +453,7 @@ Aig::Aig(Cell *cell)
 		int B = mk.inport("\\B");
 		int C = mk.inport("\\C");
 		int D = mk.inport("\\D");
-		int Y = mk.nand_gate(mk.nor_gate(A, B), mk.nor_gate(C, D));
+		int Y = mk.nand_gate(mk.or_gate(A, B), mk.or_gate(C, D));
 		mk.outport(Y, "\\Y");
 		goto optimize;
 	}
diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 89df36222..4e91eddda 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -469,7 +469,7 @@ struct CellTypes
 		if (cell->type == "$_AOI4_")
 			return eval_not(const_or(const_and(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1));
 		if (cell->type == "$_OAI4_")
-			return eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1));
+			return eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_or(arg3, arg4, false, false, 1), false, false, 1));
 
 		log_assert(arg4.bits.size() == 0);
 		return eval(cell, arg1, arg2, arg3, errp);
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc
index cfe4b4067..1fbc41082 100644
--- a/passes/opt/wreduce.cc
+++ b/passes/opt/wreduce.cc
@@ -465,12 +465,10 @@ struct WreduceWorker
 					SigSpec initsig = init_attr_sigmap(w);
 					int width = std::min(GetSize(initval), GetSize(initsig));
 					for (int i = 0; i < width; i++) {
-						log_dump(initsig[i], remove_init_bits.count(initsig[i]));
 						if (!remove_init_bits.count(initsig[i]))
 							new_initval[i] = initval[i];
 					}
 					w->attributes.at("\\init") = new_initval;
-					log_dump(w->name, initval, new_initval);
 				}
 			}
 		}
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index 50ab38063..71ce1683d 100644
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -42,7 +42,7 @@ struct dff_map_bit_info_t {
 
 bool consider_wire(RTLIL::Wire *wire, std::map<RTLIL::IdString, dff_map_info_t> &dff_dq_map)
 {
-	if (/*wire->name[0] == '$' ||*/ dff_dq_map.count(wire->name))
+	if (wire->name[0] == '$' || dff_dq_map.count(wire->name))
 		return false;
 	if (wire->port_input)
 		return false;