From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 26 Mar 2020 20:30:51 +0000 (+0000)
Subject: add TODO for cry_in==CA
X-Git-Tag: div_pipeline~1620
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9140a63ff5934fca0b938e60431e60900fc94261;p=soc.git

add TODO for cry_in==CA
---

diff --git a/src/soc/simulator/internalop_sim.py b/src/soc/simulator/internalop_sim.py
index d4c1c8d6..4afe531c 100644
--- a/src/soc/simulator/internalop_sim.py
+++ b/src/soc/simulator/internalop_sim.py
@@ -133,6 +133,8 @@ class InternalOpSimulator:
         cry_in = yield pdecode2.dec.op.cry_in
         if cry_in == CryIn.ONE.value:
             carry = 1
+        elif cry_in == CryIn.CA.value:
+            carry = TODO deliberately cause error here
 
         result = self.execute_alu_op(operand1, operand2, internal_op,
                                      carry=carry)