From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Tue, 19 Mar 2019 23:12:32 +0000 (-0700)
Subject: Fix spacing
X-Git-Tag: yosys-0.9~171^2~47
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9156e18f9215f7e8e5a36e068b137b01810769b1;p=yosys.git

Fix spacing
---

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 94a48dbc2..00a0b494b 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -76,7 +76,7 @@ module \$__SHREG_ (input C, input D, input [31:0] L, input E, output Q);
       if (&_TECHMAP_CONSTMSK_L_)
         assign Q = T4;
       else begin
-         MUXF7 fpga_mux_0 (.O(T5), .I0(T0), .I1(T2), .S(L[5]));
+        MUXF7 fpga_mux_0 (.O(T5), .I0(T0), .I1(T2), .S(L[5]));
         MUXF7 fpga_mux_1 (.O(T6), .I0(T4), .I1(1'b0 /* unused */), .S(L[5]));
         MUXF8 fpga_mux_2 (.O(Q), .I0(T5), .I1(T6), .S(L[6]));
       end