From: Luke Kenneth Casson Leighton Date: Sat, 18 Jul 2020 13:58:30 +0000 (+0100) Subject: syntax error X-Git-Tag: semi_working_ecp5~689 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=915bcfbfa1ee41478c09ca2ef0d5f9fe7a9943fa;p=soc.git syntax error --- diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py index 0adb2b0c..5eeddd5b 100644 --- a/src/soc/fu/trap/main_stage.py +++ b/src/soc/fu/trap/main_stage.py @@ -212,7 +212,7 @@ class TrapMainStage(PipeModBase): # don't understand but it's in the spec. again: bits 32-34 # are copied from srr1_i and need *restoring* to msr_i - bits = range(63-31:63-29+1) # bits 29, 30, 31 (Power notation) + bits = range(63-31,63-29+1) # bits 29, 30, 31 (Power notation) with m.If((msr_i[bits] == Const(0b010, 3)) & (srr1_i[bits] == Const(0b000, 3))): comb += msr_o.data[bits].eq(msr_i[bits])