From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 9 Jul 2020 17:07:25 +0000 (+0100)
Subject: munge alu_fsm Shifter into looking like CompALU API compliant
X-Git-Tag: div_pipeline~135
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=916163ed87d7d85e648becc119b9b79c3b20001d;p=soc.git

munge alu_fsm Shifter into looking like CompALU API compliant
---

diff --git a/src/soc/experiment/alu_fsm.py b/src/soc/experiment/alu_fsm.py
index f95c865d..98bd638b 100644
--- a/src/soc/experiment/alu_fsm.py
+++ b/src/soc/experiment/alu_fsm.py
@@ -1,7 +1,9 @@
 """Simple example of a FSM-based ALU
 
 This demonstrates a design that follows the valid/ready protocol of the
-ALU, but with a FSM implementation, instead of a pipeline.
+ALU, but with a FSM implementation, instead of a pipeline.  It is also
+intended to comply with both the CompALU API and the nmutil Pipeline API
+(Liskov Substitution Principle)
 
 The basic rules are:
 
@@ -11,10 +13,16 @@ The basic rules are:
    it accepts the input data and moves on.
 4) The FSM stays in the Done state while n.ready_i is low, otherwise
    it releases the output data and goes back to the Idle state.
+
 """
 
 from nmigen import Elaboratable, Signal, Module
 from nmigen.back.pysim import Simulator
+from soc.fu.cr.cr_input_record import CompCROpSubset
+
+
+class Dummy:
+    pass
 
 
 class Shifter(Elaboratable):
@@ -33,6 +41,17 @@ class Shifter(Elaboratable):
             self.data = Signal(width, name="p_data_i")
             self.shift = Signal(width, name="p_shift_i")
             self.dir = Signal(name="p_dir_i")
+            self.ctx = Dummy() # comply with CompALU API
+
+        def _get_data(self):
+            return [self.data, self.shift]
+
+    class NextData:
+        def __init__(self, width):
+            self.data = Signal(width, name="n_data_o")
+
+        def _get_data(self):
+            return [self.data]
 
     class PrevPort:
         def __init__(self, width):
@@ -42,7 +61,7 @@ class Shifter(Elaboratable):
 
     class NextPort:
         def __init__(self, width):
-            self.data_o = Signal(width, name="n_data_o")
+            self.data_o = Shifter.NextData(width)
             self.valid_o = Signal(name="n_valid_o")
             self.ready_i = Signal(name="n_ready_i")
 
@@ -51,6 +70,12 @@ class Shifter(Elaboratable):
         self.p = self.PrevPort(width)
         self.n = self.NextPort(width)
 
+        # more pieces to make this example class comply with the CompALU API
+        self.op = CompCROpSubset()
+        self.p.data_i.ctx.op = self.op
+        self.i = self.p.data_i._get_data()
+        self.out = self.n.data_o._get_data()
+
     def elaborate(self, platform):
         m = Module()
         # TODO: Implement Module
@@ -64,7 +89,7 @@ class Shifter(Elaboratable):
         yield self.p.ready_o
         yield self.n.ready_i
         yield self.n.valid_o
-        yield self.n.data_o
+        yield self.n.data_o.data
 
     def ports(self):
         return list(self)