From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 29 Mar 2021 18:17:56 +0000 (+0100)
Subject: add litex_ls180.mdwn
X-Git-Tag: DRAFT_SVP64_0_1~1094
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=91719c3948b4a29262545cc690ec0266da2704a5;p=libreriscv.git

add litex_ls180.mdwn
---

diff --git a/HDL_workflow/litex_ls180.mdwn b/HDL_workflow/litex_ls180.mdwn
new file mode 100644
index 000000000..cf4b7ee1c
--- /dev/null
+++ b/HDL_workflow/litex_ls180.mdwn
@@ -0,0 +1,8 @@
+# Commits for litex:
+
+the following have been identified as working with sim.py:
+
+    litex commit 35929c0f8a8f1cc098a6b6ebb569caca8df8c08d 
+    litedram commit 198bcbab676e2b4065e5b6a7dc8a7733bae8315a
+    pythondata-cpu-microwatt commit ba76652320e9dc23d9b2c64a62d0a752c870a215 
+