From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 27 Aug 2019 04:02:52 +0000 (-0700)
Subject: Missing close bracket
X-Git-Tag: working-ls180~1085^2~14
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9172d4a6740145e7b3c7c34b8fb5effd23598a94;p=yosys.git

Missing close bracket
---

diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc
index a8264cab2..b9cdbfaa1 100644
--- a/passes/pmgen/xilinx_srl.cc
+++ b/passes/pmgen/xilinx_srl.cc
@@ -213,7 +213,7 @@ struct XilinxSrlPass : public Pass {
 		log("\n");
 		log("    -variable\n");
 		log("        infer variable-length shift registers (i.e. fixed-length shifts where\n");
-		log("        each element also fans-out to a $shiftx cell.\n");
+		log("        each element also fans-out to a $shiftx cell).\n");
 		log("\n");
 	}