From: Gabe Black <gblack@eecs.umich.edu>
Date: Mon, 12 Nov 2007 22:39:14 +0000 (-0800)
Subject: X86: Fix a stupid typo where WRMSR and RDMSR were switched, and add a debug statement.
X-Git-Tag: m5_2.0_beta5~84^2~7
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=917ae9ec668fde45c8cb614d9fac29df33892fa1;p=gem5.git

X86: Fix a stupid typo where WRMSR and RDMSR were switched, and add a debug statement.

--HG--
extra : convert_revision : f1eb17291f4c01f3c0fa8f99650bc1edf09d21de
---

diff --git a/src/arch/x86/isa/insts/system/msrs.py b/src/arch/x86/isa/insts/system/msrs.py
index ea576510b..20b9b2a0b 100644
--- a/src/arch/x86/isa/insts/system/msrs.py
+++ b/src/arch/x86/isa/insts/system/msrs.py
@@ -54,7 +54,7 @@
 # Authors: Gabe Black
 
 microcode = '''
-def macroop WRMSR
+def macroop RDMSR
 {
     limm t1, "IntAddrPrefixMSR >> 3"
     ld t2, intseg, [8, t1, rcx], dataSize=8, addressSize=4
@@ -63,7 +63,7 @@ def macroop WRMSR
     mov rdx, rdx, t2, dataSize=4
 };
 
-def macroop RDMSR
+def macroop WRMSR
 {
     limm t1, "IntAddrPrefixMSR >> 3"
     mov t2, t2, rdx, dataSize=4
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 1184bf9de..dd516d2a0 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -641,6 +641,7 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
     // If this is true, we're dealing with a request to read an internal
     // value.
     if (seg == SEGMENT_REG_INT) {
+        DPRINTF(TLB, "Addresses references internal memory.\n");
         Addr prefix = vaddr & IntAddrPrefixMask;
         if (prefix == IntAddrPrefixCPUID) {
             panic("CPUID memory space not yet implemented!\n");