From: Cole Poirier <colepoirier@gmail.com>
Date: Sat, 15 Aug 2020 23:18:29 +0000 (-0700)
Subject: mmu.py fixes https://bugs.libre-soc.org/show_bug.cgi?id=450#c54
X-Git-Tag: semi_working_ecp5~329
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=918e1e838b3769ca14674865a32b9626a76c4471;p=soc.git

mmu.py fixes https://bugs.libre-soc.org/show_bug.cgi?id=450#c54
---

diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py
index df9af18c..7668234a 100644
--- a/src/soc/experiment/mmu.py
+++ b/src/soc/experiment/mmu.py
@@ -502,7 +502,7 @@ class MMU1(Elaboratable):
 #                   v.priv := l_in.priv;
                     comb += v.addr.eq(l_in.addr
                     comb += v.iside.eq(l_in.iside)
-                    comb += v.store.eq(~(l_in.load | l_in.siside))
+                    comb += v.store.eq(~(l_in.load | l_in.iside))
 #                   if l_in.tlbie = '1' then
                     with m.If(l_in.tlbie):
 #                       -- Invalidate all iTLB/dTLB entries for