From: Michael Nolan <mtnolan2640@gmail.com>
Date: Fri, 15 May 2020 16:33:39 +0000 (-0400)
Subject: Add test for cmpeqb
X-Git-Tag: div_pipeline~1193
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=91996563cf3fc3c7b9f95e370d17eecf045c84cf;p=soc.git

Add test for cmpeqb
---

diff --git a/src/soc/decoder/isa/comparefixed.patch b/src/soc/decoder/isa/comparefixed.patch
index fb058941..b80e7be4 100644
--- a/src/soc/decoder/isa/comparefixed.patch
+++ b/src/soc/decoder/isa/comparefixed.patch
@@ -1,5 +1,5 @@
---- comparefixed.py.orig	2020-05-07 14:19:47.384535384 -0400
-+++ comparefixed.py	2020-05-07 14:19:11.220806542 -0400
+--- comparefixed.py.orig	2020-05-15 10:02:00.087668937 -0400
++++ comparefixed.py	2020-05-15 12:32:36.834556205 -0400
 @@ -21,7 +21,7 @@
              c = SelectableInt(value=0x2, bits=3)
          else:
@@ -36,7 +36,7 @@
          return (CR,)
  
      @inject()
-@@ -85,10 +85,10 @@
+@@ -85,23 +85,22 @@
          else:
              in_range = le(src21lo, src1) & le(src1, src21hi) | le(src22lo, src1) & le(
                  src1, src22hi)
@@ -51,7 +51,11 @@
          return (CR,)
  
      @inject()
-@@ -98,10 +98,10 @@
+-    def op_cmpeqb(self, RB, CR):
+-        src1 = GPR[RA]
+-        src1 = src1[56:64]
++    def op_cmpeqb(self, RA, RB, CR):
++        src1 = RA[56:64]
          match = eq(src1, RB[0:8]) | eq(src1, RB[8:16]) | eq(src1, RB[16:24]) | eq(src1,
              RB[24:32]) | eq(src1, RB[32:40]) | eq(src1, RB[40:48]) | eq(src1, RB[48:56]
              ) | eq(src1, RB[56:64])
@@ -66,3 +70,12 @@
          return (CR,)
  
      comparefixed_instrs = {}
+@@ -136,7 +135,7 @@
+                 form='X',
+                 asmregs=[['BF', 'L', 'RA', 'RB']])
+     comparefixed_instrs['cmpeqb'] = instruction_info(func=op_cmpeqb,
+-                read_regs=OrderedSet(['RB']),
++                read_regs=OrderedSet(['RA', 'RB']),
+                 uninit_regs=OrderedSet(), write_regs=OrderedSet(['CR']),
+                 special_regs=OrderedSet(['CR']), op_fields=OrderedSet(['BF']),
+                 form='X',
diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index f1563472..19bff96a 100644
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -264,6 +264,17 @@ class DecoderTestCase(FHDLTestCase):
             sim = self.run_tst_program(program, initial_regs)
             self.assertEqual(sim.gpr(2), SelectableInt(16, 64))
             self.assertEqual(sim.gpr(4), SelectableInt(8, 64))
+
+    def test_cmpeqb(self):
+        lst = ["cmpeqb cr0, 2, 1",
+               "cmpeqb cr1, 3, 1"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x0102030405060708
+        initial_regs[2] = 0x04
+        initial_regs[3] = 0x10
+        with Program(lst) as program:
+            sim = self.run_tst_program(program, initial_regs)
+        
         
 
     def test_mtcrf(self):
diff --git a/src/soc/decoder/selectable_int.py b/src/soc/decoder/selectable_int.py
index ce7c2ebb..e09d8595 100644
--- a/src/soc/decoder/selectable_int.py
+++ b/src/soc/decoder/selectable_int.py
@@ -149,6 +149,8 @@ class FieldSelectableIntTestCase(unittest.TestCase):
 
 class SelectableInt:
     def __init__(self, value, bits):
+        if isinstance(value, SelectableInt):
+            value = value.value
         mask = (1 << bits) - 1
         self.value = value & mask
         self.bits = bits