From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 11 Apr 2019 15:47:36 +0000 (+0100)
Subject: reorg of FIFOtest to allow for flattening of incoming data
X-Git-Tag: ls180-24jan2020~1259
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=91a1b015f0ec82daa70e5a0bc4ef6e307b351835;p=ieee754fpu.git

reorg of FIFOtest to allow for flattening of incoming data
---

diff --git a/src/add/record_experiment.py b/src/add/record_experiment.py
index 6ecd6707..b3194962 100644
--- a/src/add/record_experiment.py
+++ b/src/add/record_experiment.py
@@ -27,7 +27,7 @@ class RecordTest:
 
         print (self.r1.fields)
         print (self.r1.shape())
-        print (len(self.r1))
+        print ("width", len(self.r1))
         m.d.comb += self.sig123.eq(flatten(self.r1))
 
         return m
diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index caaedae1..ff402c60 100644
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -351,9 +351,9 @@ class Visitor:
                 val = val[field_name] # dictionary-style specification
             val = self.visit(ao.fields[field_name], val, act)
             if isinstance(val, Sequence):
-                rres += val
+                res += val
             else:
-                rres.append(val)
+                res.append(val)
         return res
 
     def arrayproxy_visit(self, ao, ai, act):
@@ -1023,28 +1023,30 @@ class FIFOtest(ControlBase):
         Note: the only things it will accept is a Signal of width "width".
     """
 
-    def __init__(self, width, depth):
+    def __init__(self, iospecfn, width, depth):
 
-        self.fwidth = width
+        self.iospecfn = iospecfn
+        self.fwidth = width # XXX temporary
         self.fdepth = depth
-        def iospecfn():
-            return Signal(width, name="data")
-        stage = PassThroughStage(iospecfn)
-        ControlBase.__init__(self, stage=stage)
+        #stage = PassThroughStage(iospecfn)
+        ControlBase.__init__(self, stage=self)
+
+    def ispec(self): return self.iospecfn()
+    def ospec(self): return Signal(self.fwidth, name="dout")
+    def process(self, i): return i
 
     def elaborate(self, platform):
         self.m = m = ControlBase._elaborate(self, platform)
 
-        fifo = SyncFIFO(self.fwidth, self.fdepth)
+        (fwidth, _) = self.p.i_data.shape()
+        fifo = SyncFIFO(fwidth, self.fdepth)
         m.submodules.fifo = fifo
 
-        # prev: make the FIFO "look" like a PrevControl...
-        fp = PrevControl()
-        fp.i_valid = fifo.we
-        fp._o_ready = fifo.writable
-        fp.i_data = fifo.din
-        # ... so we can do this!
-        m.d.comb += fp._connect_in(self.p, True)
+        # connect the rdy/valid/data
+        m.d.comb += [fifo.we.eq(self.p.i_valid_test),
+                     self.p.o_ready.eq(fifo.writable),
+                     eq(fifo.din, flatten(self.p.i_data)),
+                   ]
 
         # next: make the FIFO "look" like a NextControl...
         fn = NextControl()
diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index b695e537..6bf690c2 100644
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -763,10 +763,14 @@ class ExampleBufPassThruPipe(ControlBase):
 # Test 20
 ######################################################################
 
+def iospecfn():
+    return Signal(16, name="din")
+
 class FIFOTest16(FIFOtest):
 
+
     def __init__(self):
-        FIFOtest.__init__(self, 16, 2)
+        FIFOtest.__init__(self, iospecfn, 16, 2)
 
 
 ######################################################################