From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 6 Mar 2020 18:20:30 +0000 (-0800)
Subject: abc9: (* keep *) wires to be PO only, not PI as well; fix scc handling
X-Git-Tag: working-ls180~763^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=91a7a74ac438ba5b030d90fcfafeb1db03757d91;p=yosys.git

abc9: (* keep *) wires to be PO only, not PI as well; fix scc handling
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 402f41597..7b6b851b3 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -174,11 +174,12 @@ struct XAigerWriter
 				undriven_bits.insert(bit);
 				unused_bits.insert(bit);
 
-				bool keep = wire->get_bool_attribute(ID::keep);
-				if (wire->port_input || keep)
+				bool scc = wire->attributes.count(ID(abc9_scc));
+				if (wire->port_input || scc)
 					input_bits.insert(bit);
 
-				if (wire->port_output || keep) {
+				bool keep = wire->get_bool_attribute(ID::keep);
+				if (wire->port_output || keep || scc) {
 					if (bit != wirebit)
 						alias_map[wirebit] = bit;
 					output_bits.insert(wirebit);
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index b0bd81698..27e9fd239 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -110,14 +110,13 @@ void mark_scc(RTLIL::Module *module)
 			if (c.second.is_fully_const()) continue;
 			if (cell->output(c.first)) {
 				SigBit b = c.second.as_bit();
+				// TODO: Don't be as heavy handed as to
+				//       mark the entire wire as part of the scc
 				Wire *w = b.wire;
-				w->set_bool_attribute(ID::keep);
-				w->attributes[ID(abc9_scc_id)] = id.as_int();
+				w->set_bool_attribute(ID(abc9_scc));
 			}
 		}
 	}
-
-	module->fixup_ports();
 }
 
 void prep_dff(RTLIL::Module *module)
@@ -967,10 +966,8 @@ void reintegrate(RTLIL::Module *module)
 		RTLIL::Wire *mapped_wire = mapped_mod->wire(port);
 		RTLIL::Wire *wire = module->wire(port);
 		log_assert(wire);
-		if (wire->attributes.erase(ID(abc9_scc_id))) {
-			auto r YS_ATTRIBUTE(unused) = wire->attributes.erase(ID::keep);
-			log_assert(r);
-		}
+		wire->attributes.erase(ID(abc9_scc));
+
 		RTLIL::Wire *remap_wire = module->wire(remap_name(port));
 		RTLIL::SigSpec signal(wire, 0, GetSize(remap_wire));
 		log_assert(GetSize(signal) >= GetSize(remap_wire));