From: Bas Nieuwenhuizen Date: Mon, 16 Oct 2017 16:09:25 +0000 (+0200) Subject: radv: Update GFX9 user data regs for GS/tess. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=91b033f4f6055f7ead57c8d6c454288b0b827257;p=mesa.git radv: Update GFX9 user data regs for GS/tess. Reviewed-by: Dave Airlie --- diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 147235006fa..e07a6e7c1fe 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -503,7 +503,7 @@ radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer, int idx, uint64_t va) { struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx); - uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline)); + uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline)); if (loc->sgpr_idx == -1) return; assert(loc->num_sgprs == 2); @@ -545,7 +545,7 @@ radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer, if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) { uint32_t offset; struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET); - uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline)); + uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline)); if (loc->sgpr_idx == -1) return; assert(loc->num_sgprs == 1); @@ -764,7 +764,7 @@ radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer, loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT); if (loc->sgpr_idx != -1) { - uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline)); + uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline)); assert(loc->num_sgprs == 4); assert(!loc->indirect); radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4); @@ -777,7 +777,7 @@ radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer, loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT); if (loc->sgpr_idx != -1) { - uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline)); + uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline)); assert(loc->num_sgprs == 1); assert(!loc->indirect); @@ -787,7 +787,7 @@ radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer, loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT); if (loc->sgpr_idx != -1) { - uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline)); + uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline)); assert(loc->num_sgprs == 1); assert(!loc->indirect); @@ -1487,7 +1487,7 @@ emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer, gl_shader_stage stage) { struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx]; - uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline)); + uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline)); if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect) return; @@ -2858,7 +2858,7 @@ static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned in struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX); if (loc->sgpr_idx == -1) continue; - uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline)); + uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline)); radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index); } diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 4f840d156fa..16e4b307e65 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2022,7 +2022,7 @@ radv_pipeline_init(struct radv_pipeline *pipeline, struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_BASE_VERTEX_START_INSTANCE); if (loc->sgpr_idx != -1) { - pipeline->graphics.vtx_base_sgpr = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline)); + pipeline->graphics.vtx_base_sgpr = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline)); pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4; if (pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id) pipeline->graphics.vtx_emit_num = 3; diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index ed76e1d0242..a7836543998 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -500,24 +500,35 @@ radv_shader_variant_destroy(struct radv_device *device, } uint32_t -radv_shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, - bool has_tess) +radv_shader_stage_to_user_data_0(gl_shader_stage stage, enum chip_class chip_class, + bool has_gs, bool has_tess) { switch (stage) { case MESA_SHADER_FRAGMENT: return R_00B030_SPI_SHADER_USER_DATA_PS_0; case MESA_SHADER_VERTEX: + if (chip_class >= GFX9) { + return has_tess ? R_00B430_SPI_SHADER_USER_DATA_LS_0 : + has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : + R_00B130_SPI_SHADER_USER_DATA_VS_0; + } if (has_tess) return R_00B530_SPI_SHADER_USER_DATA_LS_0; else return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0; case MESA_SHADER_GEOMETRY: - return R_00B230_SPI_SHADER_USER_DATA_GS_0; + return chip_class >= GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : + R_00B230_SPI_SHADER_USER_DATA_GS_0; case MESA_SHADER_COMPUTE: return R_00B900_COMPUTE_USER_DATA_0; case MESA_SHADER_TESS_CTRL: - return R_00B430_SPI_SHADER_USER_DATA_HS_0; + return chip_class >= GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 : + R_00B430_SPI_SHADER_USER_DATA_HS_0; case MESA_SHADER_TESS_EVAL: + if (chip_class >= GFX9) { + return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : + R_00B130_SPI_SHADER_USER_DATA_VS_0; + } if (has_gs) return R_00B330_SPI_SHADER_USER_DATA_ES_0; else diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index 952594a18e0..27dd87f7ae6 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -104,8 +104,8 @@ radv_shader_variant_destroy(struct radv_device *device, struct radv_shader_variant *variant); uint32_t -radv_shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, - bool has_tess); +radv_shader_stage_to_user_data_0(gl_shader_stage stage, enum chip_class chip_class, + bool has_gs, bool has_tess); const char * radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage);