From: Brad Beckmann <Brad.Beckmann@amd.com>
Date: Mon, 22 Mar 2010 04:22:20 +0000 (-0700)
Subject: ruby: Python config files now sets a unique id for each sequencer
X-Git-Tag: stable_2012_02_02~1467
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=91b0c5487bcf0259eab25baef686fbef83adae1a;p=gem5.git

ruby: Python config files now sets a unique id for each sequencer
---

diff --git a/configs/ruby/MESI_CMP_directory.py b/configs/ruby/MESI_CMP_directory.py
index 8ae2be2fa..ca5a7aa46 100644
--- a/configs/ruby/MESI_CMP_directory.py
+++ b/configs/ruby/MESI_CMP_directory.py
@@ -76,7 +76,8 @@ def create_system(options, phys_mem, piobus, dma_devices):
         l1d_cache = L1Cache(size = options.l1d_size,
                             assoc = options.l1d_assoc)
 
-        cpu_seq = RubySequencer(icache = l1i_cache,
+        cpu_seq = RubySequencer(version = i,
+                                icache = l1i_cache,
                                 dcache = l1d_cache,
                                 physMemPort = phys_mem.port,
                                 physmem = phys_mem)
diff --git a/configs/ruby/MI_example.py b/configs/ruby/MI_example.py
index 971a52dc8..96515971e 100644
--- a/configs/ruby/MI_example.py
+++ b/configs/ruby/MI_example.py
@@ -71,7 +71,8 @@ def create_system(options, phys_mem, piobus, dma_devices):
         #
         # Only one unified L1 cache exists.  Can cache instructions and data.
         #
-        cpu_seq = RubySequencer(icache = cache,
+        cpu_seq = RubySequencer(version = i,
+                                icache = cache,
                                 dcache = cache,
                                 physMemPort = phys_mem.port,
                                 physmem = phys_mem)
diff --git a/configs/ruby/MOESI_CMP_directory.py b/configs/ruby/MOESI_CMP_directory.py
index 6e248573d..1cdb6c522 100644
--- a/configs/ruby/MOESI_CMP_directory.py
+++ b/configs/ruby/MOESI_CMP_directory.py
@@ -76,7 +76,8 @@ def create_system(options, phys_mem, piobus, dma_devices):
         l1d_cache = L1Cache(size = options.l1d_size,
                             assoc = options.l1d_assoc)
 
-        cpu_seq = RubySequencer(icache = l1i_cache,
+        cpu_seq = RubySequencer(version = i,
+                                icache = l1i_cache,
                                 dcache = l1d_cache,
                                 physMemPort = phys_mem.port,
                                 physmem = phys_mem)
diff --git a/configs/ruby/MOESI_CMP_token.py b/configs/ruby/MOESI_CMP_token.py
index 8d7f7a354..849d5b62a 100644
--- a/configs/ruby/MOESI_CMP_token.py
+++ b/configs/ruby/MOESI_CMP_token.py
@@ -82,7 +82,8 @@ def create_system(options, phys_mem, piobus, dma_devices):
         l1d_cache = L1Cache(size = options.l1d_size,
                             assoc = options.l1d_assoc)
 
-        cpu_seq = RubySequencer(icache = l1i_cache,
+        cpu_seq = RubySequencer(version = i,
+                                icache = l1i_cache,
                                 dcache = l1d_cache,
                                 physMemPort = phys_mem.port,
                                 physmem = phys_mem)
diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py
index 62d86a1e2..17fcefb56 100644
--- a/configs/ruby/MOESI_hammer.py
+++ b/configs/ruby/MOESI_hammer.py
@@ -77,7 +77,8 @@ def create_system(options, phys_mem, piobus, dma_devices):
         l2_cache = L2Cache(size = options.l2_size,
                            assoc = options.l2_assoc)
 
-        cpu_seq = RubySequencer(icache = l1i_cache,
+        cpu_seq = RubySequencer(version = i,
+                                icache = l1i_cache,
                                 dcache = l1d_cache,
                                 physMemPort = phys_mem.port,
                                 physmem = phys_mem)