From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 9 Jul 2020 19:00:29 +0000 (+0100)
Subject: simplify setting of mul overflow into xer_ov
X-Git-Tag: div_pipeline~130
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=91b0cf7d6faa06b6675bebbdcedda9eb8a6019ff;p=soc.git

simplify setting of mul overflow into xer_ov
---

diff --git a/src/soc/fu/mul/post_stage.py b/src/soc/fu/mul/post_stage.py
index b200aa8f..9f3d6963 100644
--- a/src/soc/fu/mul/post_stage.py
+++ b/src/soc/fu/mul/post_stage.py
@@ -45,6 +45,7 @@ class MulMainStage3(PipeModBase):
                 comb += o.data.eq(mul_o[64:128])
             # lo-64 - overflow
             with m.Default():
+                # take the low 64 bits of the mul
                 comb += o.data.eq(mul_o[0:64])
 
                 # compute overflow
@@ -56,11 +57,8 @@ class MulMainStage3(PipeModBase):
                     m64 = mul_o[64:128]
                     comb += mul_ov.eq(m64.bool() & ~m64.all())
 
-                # 32-bit (ov[1]) and 64-bit (ov[0]) overflow
-                ov = Signal(2, reset_less=True)
-                comb += ov[0].eq(mul_ov)
-                comb += ov[1].eq(mul_ov)
-                comb += ov_o.data.eq(ov)
+                # 32-bit (ov[1]) and 64-bit (ov[0]) overflow - both same
+                comb += ov_o.data.eq(Repl(mul_ov, 2)) # sets OV _and_ OV32
                 comb += ov_o.ok.eq(1)
 
         ###### sticky overflow and context, both pass-through #####