From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 5 May 2019 13:40:47 +0000 (+0100)
Subject: add SRlatch async mode
X-Git-Tag: ls180-24jan2020~1029
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=91c103fd5d1e3cb88d053b093aef61a98d6b4fc1;p=ieee754fpu.git

add SRlatch async mode
---

diff --git a/src/nmutil/latch.py b/src/nmutil/latch.py
index dbdb23e5..41a8df94 100644
--- a/src/nmutil/latch.py
+++ b/src/nmutil/latch.py
@@ -4,7 +4,8 @@ from nmigen import Signal, Module, Elaboratable
 
 
 class SRLatch(Elaboratable):
-    def __init__(self):
+    def __init__(self, sync=True):
+        self.sync = sync
         self.s = Signal(reset_less=True)
         self.r = Signal(reset_less=True)
         self.q = Signal(reset_less=True)
@@ -14,13 +15,25 @@ class SRLatch(Elaboratable):
         m = Module()
         q_int = Signal(reset_less=True)
 
-        with m.If(self.s):
-            m.d.sync += q_int.eq(1)
-        with m.Elif(self.r):
-            m.d.sync += q_int.eq(0)
-
-        m.d.comb += self.q.eq(q_int)
-        m.d.comb += self.qn.eq(~q_int)
+        if self.sync:
+            with m.If(self.s):
+                m.d.sync += q_int.eq(1)
+            with m.Elif(self.r):
+                m.d.sync += q_int.eq(0)
+            m.d.comb += self.q.eq(q_int)
+            m.d.comb += self.qn.eq(~q_int)
+        else:
+            with m.If(self.s):
+                m.d.sync += q_int.eq(1)
+                m.d.comb += self.q.eq(1)
+                m.d.comb += self.qn.eq(0)
+            with m.Elif(self.r):
+                m.d.sync += q_int.eq(0)
+                m.d.comb += self.q.eq(0)
+                m.d.comb += self.qn.eq(1)
+            with m.Else():
+                m.d.comb += self.q.eq(q_int)
+                m.d.comb += self.qn.eq(~q_int)
 
         return m
 
diff --git a/src/scoreboard/int_fn_unit.py b/src/scoreboard/int_fn_unit.py
index 93f95be3..ca8bc1a2 100644
--- a/src/scoreboard/int_fn_unit.py
+++ b/src/scoreboard/int_fn_unit.py
@@ -38,8 +38,8 @@ class IntFnUnit(Elaboratable):
 
     def elaborate(self, platform):
         m = Module()
-        m.submodules.rd_l = rd_l = SRLatch()
-        m.submodules.wr_l = wr_l = SRLatch()
+        m.submodules.rd_l = rd_l = SRLatch(sync=False)
+        m.submodules.wr_l = wr_l = SRLatch(sync=False)
         m.submodules.dest_d = dest_d = Decoder(self.reg_width)
         m.submodules.src1_d = src1_d = Decoder(self.reg_width)
         m.submodules.src2_d = src2_d = Decoder(self.reg_width)