From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 13 Jun 2018 07:45:27 +0000 (+0100)
Subject: update
X-Git-Tag: convert-csv-opcode-to-binary~5215
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=91c21db2f5dcf2e43068c7aa45535228ed8c7dc0;p=libreriscv.git

update
---

diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn
index 0c0dde765..803bdba02 100644
--- a/simple_v_extension.mdwn
+++ b/simple_v_extension.mdwn
@@ -1,14 +1,5 @@
 # Variable-width Variable-packed SIMD / Simple-V / Parallelism Extension Proposal
 
-* TODO 23may2018: CSR-CAM-ify regfile tables
-* TODO 23may2018: zero-mark predication CSR
-* TODO 28may2018: sort out VSETVL: CSR length to be removed?
-* TODO 09jun2018: Chennai Presentation more up-to-date
-* TODO 09jun2019: elwidth only 4 values (dflt, dflt/2, 8, 16)
-* TODO 09jun2019: extra register banks (future option)
-* TODO 09jun2019: new Reg CSR table (incl. packed=Y/N)
-
-
 Key insight: Simple-V is intended as an abstraction layer to provide
 a consistent "API" to parallelisation of existing *and future* operations.
 *Actual* internal hardware-level parallelism is *not* required, such