From: lkcl <lkcl@web>
Date: Fri, 6 Aug 2021 15:39:57 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~470
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=91cbb5e335867813ab41f8f01b22f4e7b80863d5;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index a467de30d..bafb0b57b 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -208,7 +208,7 @@ for srcstep in range(VL):
     else
         cond_ok |= el_cond_ok
     # test for VL to be set (and exit)
-    if ~el_cond_ok and VLSET
+    if VLSET and VSb = el_cond_ok then
         if SVRMmode.VLI
             SVSTATE.VL = srcstep+1
         else
@@ -247,7 +247,7 @@ else
 # actual element test here
 cond_ok <- BO[0] | ¬(testbit ^ BO[1])
 # test for VL to be set (and exit)
-if ~cond_ok and VLSET
+if VLSET and cond_ok = VSb then
     if SVRMmode.VLI
         SVSTATE.VL = new_srcstep+1
     else