From: Clifford Wolf Date: Thu, 6 Feb 2014 21:09:21 +0000 (+0100) Subject: Added copy command X-Git-Tag: yosys-0.2.0~59 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=91eab69912a3add35919417b59e6944a27596218;p=yosys.git Added copy command --- diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc index 8020adff6..a5a386595 100644 --- a/passes/cmds/Makefile.inc +++ b/passes/cmds/Makefile.inc @@ -11,4 +11,5 @@ OBJS += passes/cmds/setundef.o OBJS += passes/cmds/splitnets.o OBJS += passes/cmds/stat.o OBJS += passes/cmds/setattr.o +OBJS += passes/cmds/copy.o diff --git a/passes/cmds/copy.cc b/passes/cmds/copy.cc new file mode 100644 index 000000000..4b1a8db81 --- /dev/null +++ b/passes/cmds/copy.cc @@ -0,0 +1,54 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/register.h" +#include "kernel/rtlil.h" +#include "kernel/log.h" + +struct CopyPass : public Pass { + CopyPass() : Pass("copy", "copy modules in the design") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" copy old_name new_name\n"); + log("\n"); + log("Copy the specified module. Note that selection patterns are not supported\n"); + log("by this command.\n"); + log("\n"); + } + virtual void execute(std::vector args, RTLIL::Design *design) + { + if (args.size() != 3) + log_cmd_error("Invalid number of arguments!\n"); + + std::string src_name = RTLIL::escape_id(args[1]); + std::string trg_name = RTLIL::escape_id(args[2]); + + if (design->modules.count(src_name) == 0) + log_cmd_error("Can't find source module %s.\n", src_name.c_str()); + + if (design->modules.count(trg_name) != 0) + log_cmd_error("Target module name %s already exists.\n", trg_name.c_str()); + + design->modules[trg_name] = design->modules.at(src_name)->clone(); + design->modules[trg_name]->name = trg_name; + } +} CopyPass; +