From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 31 Jul 2019 20:39:13 +0000 (+0100)
Subject: move assignment into out_do_z condition
X-Git-Tag: ls180-24jan2020~601
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=91f9a4d2614cb6c28b122431b4091505fe5f8261;p=ieee754fpu.git

move assignment into out_do_z condition
---

diff --git a/src/ieee754/fpadd/add0.py b/src/ieee754/fpadd/add0.py
index e5845b44..2110f81b 100644
--- a/src/ieee754/fpadd/add0.py
+++ b/src/ieee754/fpadd/add0.py
@@ -34,14 +34,13 @@ class FPAddStage0Mod(PipeModBase):
         mge = Signal(reset_less=True)
         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
-        comb += [seq.eq(self.i.a.s == self.i.b.s),
-                 mge.eq(self.i.a.m >= self.i.b.m),
-                 am0.eq(Cat(self.i.a.m, 0)),
-                 bm0.eq(Cat(self.i.b.m, 0))
-                ]
-
         # same-sign (both negative or both positive) add mantissas
         with m.If(~self.i.out_do_z):
+            comb += [seq.eq(self.i.a.s == self.i.b.s),
+                     mge.eq(self.i.a.m >= self.i.b.m),
+                     am0.eq(Cat(self.i.a.m, 0)),
+                     bm0.eq(Cat(self.i.b.m, 0))
+                    ]
             comb += self.o.z.e.eq(self.i.a.e)
             with m.If(seq):
                 comb += [